Samsung Electronics Co., Ltd.

Mi-Jo Kim

Soo-Young Kim

Chang-Ho Lee

Young-Min Lee

Dong-Hyuk Lee

Jong-hyun Choi

Ho-Cheol Lee

Jung-Sik Kim

Jong-Wook Park

Kwang-Sook Noh

Han-Gu Sohn

Eun-sung Seo

Beob-Rae Cho

Yun-Hee Shin

Jung-Soo Ryoo

A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a first processor configured to exchange data with a first data length format, a second processor configured to exchange data with a second data length format and a shared memory configured to store data, the shared memory being shared by the first and second processors, the shared memory further configured to receive a read command from at least one of the first and second processors and to output data in response to the read command based on which of the first and second data length formats is used by the processor issuing the read command.

Semiconductor memory device inputting and outputting a plurality of data length formats and method thereof

A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

Multipath accessible semiconductor memory device with host interface between processors

Embodiments of the invention provide a semiconductor chip and a semiconductor chip package comprising a semiconductor chip. In one embodiment, the invention provides a semiconductor chip comprising a memory cell array, a control circuit, and a chip selection signal generating circuit electrically connected to first and second option pads. In the semiconductor chip, the chip selection signal generating circuit is enabled in accordance with a dual chip enable signal, and the control circuit is enabled and disabled in accordance with the chip selection signal received from the chip selection signal generating circuit. In addition, the chip selection signal generating circuit is adapted to generate a chip selection signal in accordance with signals received through the first and second option pads, respectively.

Semiconductor chip and semiconductor chip package comprising semiconductor chip

A semiconductor device includes a memory and a power voltage interrupter configured to interrupt an external power voltage applied to circuitry of the semiconductor device responsive to a Deep Power Down (DPD) command signal generated in a DPD mode of the memory. A power voltage shifter is configured to shift a power voltage in the circuitry to a specific level responsive to the DPD command signal.

Semiconductor devices including an external power voltage control function and methods of operating the same

Growing community of inventors

Suwon-si, South Korea

Mi-Jo Kim