Samsung Electronics Co., Ltd.

Seoul National University

Mi-Hyun Kang

Hwa-Sook Shin

Mueng-Ryul Lee

Yong-Hoan Kim

In-Ah Kim

Min-Guk Han

Meung-Ryul Lee

Won-Ick Chang

Bum-Sup Jang

The present invention provides a pharmaceutical composition and a treatment method to be combined with radiotherapy, for treatment of triple negative breast cancer. More specifically, the pharmaceutical composition comprises a PD-1 blockade and a PI3K&#x3b3; &#x3b4; inhibitor, and it has excellent effects of inhibiting tumor and enhancing immunity by combining the PD-1 blockade and PI3K&#x3b3; &#x3b4; inhibitor with radiotherapy, compared to single therapy of each therapeutic agent.

Method of treating metastatic triple negative breast cancer with radiotherapy combined with phosphatidyl inositol-3 kinase delta/gamma inhibitors and anti-PD-1 antibodies

Provided are an apparatus and a method for simulating a semiconductor device. The method includes: modeling, through an input interface of a simulation device, a flat transistor as a first transistor; modeling, through the input interface, a first corner transistor as a second transistor; and calculating, by a processor of the simulation device, an output electrical signal in response to an input electrical signal applied to the first transistor and the second transistor to simulate at least one electrical characteristic of the semiconductor device. The flat transistor is formed by an active region defined by an isolation region on a semiconductor substrate, a gate electrode extending from the isolation region across the active region, and an impurity region in a portion of the active region. The first corner transistor is formed by an overlapping of the gate electrode and a first edge portion of the active region.

Method of simulating semiconductor devices and method of designing semiconductor devices using the same

A semiconductor integrated circuit device includes a first dopant region in a semiconductor substrate, an isolation region on the semiconductor substrate, the isolation region surrounding the first dopant region, a gate wire surrounding at least a portion of the isolation region, and a plurality of second dopant regions arranged along at least a portion of the gate wire, the plurality of second dopant regions being spaced apart from each other, and the portion of the gate wire being between the first dopant region and a respective second dopant region.

Semiconductor integrated circuit device and method of manufacturing the same

In a HV transistor having a high breakdown voltage and a method of manufacturing the same, a first insulation pattern is formed on a semiconductor substrate by oxidizing a portion of the substrate, and a second insulation pattern is formed such that at least a portion of the first insulation pattern is covered with the second insulation pattern. A gate electrode including a first end portion and a second end portion opposite to the first end portion is formed on the substrate by depositing conductive materials onto the substrate. The first end portion is formed on the first insulation pattern and the second end portion is formed on the second insulation pattern. Source/drain regions are formed at surface portions of the substrate by implanting impurities onto the substrate. Electric field intensity at an edge portion of the gate electrode is reduced, and the HV transistor has a high breakdown voltage.

Growing community of inventors

Seongnam-si, South Korea

Mi-Hyun Kang