Taiwan Semiconductor Manufacturing Comp. Ltd.

Texas Instruments Corporation

Mi-Chang Chang

Li-Chun Tien

Li-Jui Chen

Tsai-Sheng Gau

Chun-Kuang Chen

Thomas J Aton

Jaw-Jung Shin

Burn-Jeng Lin

Huan-Tsung Huang

Jan-Wen You

Liang-Kai Han

Jen-Hang Yang

King-Chang Shu

Wen-Jya Liang

Su-Ya Lin

Yu-Jun Chou

This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (Ms) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.

Method for automatically modifying integrated circuit layout

A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

Transistor layout for standard cell with optimized mechanical stress effect

A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

Method of defining forbidden pitches for a lithography exposure tool

A method for evaluating a mask pattern for a product that is manufactured by a process that is described at least in part by a mathematical process model includes the steps of: (a) selecting a reference locus; (b) determining a sampling direction from the reference locus; (c) selecting a sampling locus in the sampling direction; (d) evaluating a model factor at the sampling locus; and (e) applying at least one predetermined criterion to the model factor to determine a conclusion. If the conclusion is a first inference, (f) repeating steps (c) through (e). If the conclusion is a second inference, (g) determining whether the evaluation is complete and repeating steps (a) through (g) until the evaluating is complete.

Method for evaluating a mask pattern on a substrate

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Hsinchu, Taiwan

Mi-Chang Chang