Skhynix Inc.

Meysam Asadi

Fan Zhang

Haobo Wang

Xuanxuan Lu

Aman Bhatia

Chenrong Xiong

Hongwei Duan

Jianqing Chen

Ahmad Golmohammadi

Teodor Vlasov

Qiuju Diao

Seyhan Karakulak

Techniques for decoding a low-density parity check (LDPC) can include determining an asymmetric ratio of bit errors read as logic zero to bit errors read as logic one. The energy of each variable node of the LDPC codeword can be computed. For each variable node having an energy greater than a threshold energy, the variable node can be added to a collection of candidate bits for bit flipping. The asymmetric ratio can then be applied to flip bits in the collection of candidate bits to decode the LDPC codeword.

Error correction based on asymmetric ratio

A memory system and method for data reclaim which reads data from a memory using a preset voltage threshold based on a page type being read; records an initial set of program voltages for successful reads of the data from the memory; determines an initial distribution of the initial set of program voltages, over time subsequent sets of the program voltages for successful reads of the data from the memory; determines subsequent distributions of the subsequent sets of the program voltages; and based on program voltage variations of the subsequent distributions from the initial deviation, recycles the data in the memory.

PV distribution variation detection and data reclaim policy

A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: decode codewords in the memory block; determine failed codewords based on one or more parity checks including a chipkill parity; and turbo-decode the failed codewords using at least two decoders in a feedback loop with adders prior to each decoder for scaling soft decode information prior to subsequent decoding of the failed codewords.

Data recovery with enhanced super chip-kill recovery and method of operating such memory system

Devices, systems, and methods for improving performance of an iterative decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular low-density parity-check (LDPC) code, performing, in a first mode of the iterative decoder and on the noisy codeword for a number of iterations, a message passing algorithm between multiple variable nodes and multiple check nodes that represent a parity matrix of the irregular LDPC code, and determining, subsequent to performing the number of iterations, a candidate version of the transmitted codeword. In this first mode, and as part of performing the message passing algorithm, at least one check node of the multiple check nodes is configured to store a portion of multiple check node parameters instead of all of the multiple check node parameters.

Min-sum decoding for irregular low-density parity check codes in memory devices

A bit-flipping (BF) decoder and a decoding method based on a super node, which groups two or more component nodes corresponding to two or more bits in a codeword to generate a super node; and performs a decoding iteration on the super node. The decoding iteration includes: calculating a flipping energy for the super node based on a flipping energy for each of the component nodes and internal checks between the component nodes; and flipping at least one of the two or more bits in the super node upon a determination that the flipping energy for the super node exceeds a bit-flipping threshold.

Bit-flipping decoder and decoding method based on super node

Decoding method and memory system which group bits in irregular LDPC codes having similar degrees of convergence into respective degree groups, classify the degree groups according to a metric indicative of a number of decoding iterations for convergence, divide a time period for convergence of the decoding iterations into different zones for the processing of selected degree groups within each zone, and skip decoding of the bits in a non-converging zone where the bits are not converging.

Method and system for fast column processing for highly irregular LDPC codes

Devices, systems, and methods for improving performance of an iterative decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, performing, on the noisy codeword for a first number of iterations, a message passing algorithm between a plurality of variable nodes and a plurality of check nodes that represent a parity matrix of the LDPC code, assigning, based on comparing an asymmetric ratio to a threshold, a set of asymmetric LLRs to a set of LLRs (that were initialized using symmetric LLRs) used in the message passing algorithm, and determining, subsequent to performing the message passing algorithm on the noisy codeword for a second number of iterations, a candidate version of the transmitted codeword.

Machine-learning assisted decoder with asymmetric ratio tracking in non-volatile memory devices

A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: decode codewords from the memory block, identify failed codewords from the decoded codewords, estimate raw bit errors RBERs of the failed codewords, sort failed codewords from a failed sector of the memory block in order from a first set of the failed codewords in the failed sector having a higher probability of being successfully decoded to a second set of the failed codewords in the failed sector having a lower probability of being successfully decoded, and perform a super chip kill SCK operation on one of the failed codewords in the first set to produce a recovered codeword.

Selective decoding for super chip-kill recovery and method of operating such memory system

A memory system or a method for estimating channel information to be used for error decoding. The memory system or the method a) performs one or more read operations on a page selected from among the plurality of pages using a target read threshold, b) obtains the target read threshold, a historical read threshold voltage set associated with failed read operations of the selected page, checksum values, and asymmetric ratios of ones count and zeros count which are associated with the historical read threshold voltage set, c) provides the obtained target read threshold, historical read threshold voltage set, checksum values and asymmetric ratios as input information to a neural network, and d) predicts, by the neural network, channel information at the target read threshold based on the input information and a set activation function.

System and method for history-based non-parametric channel information prediciton using a deep neural network

Decoding method and memory system that classify check nodes in a matrix having irregular check node weights into different groups according to the check node weights, apply different scaling factors to respective constant node to variable node (C2V) messages in the different groups of the check nodes, and optionally add a compensation term to at least one of the C2V messages of the MS decoder.

Min-sum decoder for row-irregular low density parity check codes

A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: read and decode codewords from the memory block, determine a fail bit count (FBC), a strong correct (SC) rate indicating a percentage of failed bits correctable through log likelihood ratios (LLRs), and a number of spare bytes in the codewords decoded from the memory, predict a soft decoding error based on a fixed FBC, a fixed SC rate, and the number of spare bytes, and determine soft errors in the codewords read from the memory block based on the predicted soft decoding error.

Soft decoding error prediction

Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.

Out-of-order bit-flipping decoders for non-volatile memory devices

A memory system for detecting hard errors. The memory system has a first memory block and a second memory block and a memory controller in communication with the first memory block, The memory controller includes a hard error tracker module comprising hardware configured to track over time fail bit counts from data read from the first memory block and includes a hard error percentage module programmed to determine, based on the fail bit counts, hard error percentages for the data read from the first memory block. The hard error percentage module is programmed to dynamically reorder historical read retry (HRR) entries for subsequent data reads, based on a page type of the data being read and the hard error percentages determined during reading of data from the memory block.

Hard error tracker and HRR dynamic reordering

A scheme for determining a flipping energy used in a bit-flipping decoder. The flipping energy is determined based on: a weight of at least one check node coupled to a column; a syndrome as a product of a noisy codeword and a parity check matrix; and a hard decision value of a previous iteration and a channel output value associated with the column.

Bit-flipping decoder and decoding method for irregular codes

A controller estimates optimal read threshold values for a memory device using deep learning. The memory device includes multiple pages coupled to select word lines in a memory region. The controller performs multiple read operations on a select type of page for each word line using multiple read threshold sets, obtains fail bit count (FBC) information associated with each read operation, and determines an optimal read threshold set for each word line based on the FBC information. When optimal read threshold sets for the select word lines are different each other, the controller predicts a best read threshold set using the optimal read threshold sets.

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Fremont, CA, United States of America

Meysam Asadi