Intel Corporation

Mesut A Ergin

Jr-Shian Tsai

Tsung-Yuan Charles Tai

Ren Wang

Alexander W Min

Andrew J Herdrich

Prakash N Iyer

Rajesh M Sankaran

Bruce L Fleming

Jun Nakajima

Ravi L Sahita

Kapil Sood

Gilbert A Neiger

Barry E Huntley

Christian Maciocco

Wei Wang

Christopher J Hughes

David J Harriman

Ravishankar Iyer

Yen-Cheng Liu

Scott P Dubal

Herbert H Hum

Jong Soo Park

Zeshan A Chishti

Edwin Verplanke

Rajeev D Muralidhar

Harinarayanan Seshadri

Brian J Skerry

Aamer Jaleel

Namakkal N Venkatesan

Adrian C Moga

Nrupal R Jani

Ping Yu

John R Fastabend

Jeffrey B Shaw

Janet Tseng

Shinae Woo

Ashish V Choubal

Andrew D Henroid

Michael Mesnier

Cunming Liang

David E Cohen

Rashmin N Patel

Wei Shen

Xiaowen Zhang

Bo Cui

Declan W Doherty

Weishuang Zhao

Xuekun Hu

Huawei Xie

Rajith K Mavila

Yuwei Zhang

Xiaobing Qian

Lin Luo

Shravan Nagraj

Jr Brian J Skerry

Andrew W Min

A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

Aperture access processors, methods, systems, and instructions

In some examples, for process-to-process communication, such as in function linking, a virtual channel can be provisioned to provide virtual machine to virtual machine communications. In response to a transmit request from a source virtual machine, the virtual channel can cause a data copy from a source buffer associated with the source virtual machine without decryption or encryption. The virtual channel provisions a key identifier for the copied data. The destination virtual machine can receive an indication data is available and can cause the data to be decrypted using a key accessed using the key identifier and source address of the copied data. In addition, the data can be encrypted using a second, different key for storage in a destination buffer associated with the destination virtual machine. In some examples, the key identifier and source address is managed by the virtual channel and is not visible to virtual machine or hypervisor.

Process-to-process secure data movement in network functions virtualization infrastructures

Methods and apparatus for secure networking protocol optimization via NIC hardware offloading. Under a method, security offload entries are cached in a flow table or a security database offload table on a network interface coupled to a host that implements a host security database mapping flows to Security Association (SA) contexts. Each security offload entry includes information identify a flow and information, such as an offset value, to locate a corresponding entry for the flow in the host security database. Hardware descriptors for received packets that belong to flows with matching security offload entries are generated and marked with the information used to locate the corresponding entries in the host security database. The hardware descriptors are processed by software on the host and the location information is used to de-reference the location of applicable entries in the host security database.

Secure networking protocol optimization via NIC hardware offloading

Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

Processor and method implementing a cacheline demote machine instruction

Technologies for managing paravirtual network device queue and memory of a network computing device that includes multi-core processor, a multi-layer cache, a host, and a plurality of virtual machine instances. The host is assigned a processor core of the processor and may be configured to copy a received network packet to a last level cache of the multi-layer cache and determine one or more virtual machine instances configured to process the received network packet. Each virtual machine instance has been assigned a processor core of the processor and has been allocated a first level cache of the multi-level cache memory associated with the respective processor core. The host is additionally configured to inject an interrupt into each processor core of the determined virtual machine (s) which indicates to the virtual machine instance (s) that the received network packet is available to be processed.

Technologies for paravirtual network device queue and memory management

Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads

Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.

Interrupts between virtual machines

Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets between pairs of VMs within a communications server. An apparatus may include a processor component; a network interface to couple the processor component to a network; a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through the network and the communications server, and to route the set of packets through one or more virtual servers of multiple virtual servers based on the contents; and a transfer component of a first virtual server of the multiple virtual servers to determine whether to route the set of packets to the virtual switch or to transfer the set of packets to a second virtual server of the multiple virtual servers in a manner that bypasses the virtual switch based on a routing rule.

Techniques for routing packets between virtual machines

Technologies for distributed detection of security anomalies include a computing device to establish a trusted relationship with a security server. The computing device reads one or more packets of at least one of an inter-virtual network function network or an inter-virtual network function component network in response to establishing the trusted relationship and performs a security threat assessment of the one or more packets. The computing device transmits the security threat assessment to the security server.

Technologies for distributed detection of security anomalies

Various embodiments are generally directed to techniques for improving the efficiency of exchanging packets among multiple VMs within a communications server, and between the communications server and other devices in a communications system. An apparatus may include a virtual switch to analyze contents of at least one packet of a set of packets to be exchanged between endpoint devices through a network, and to correlate the contents to a pathway to extend through one or more of the VMs that are each configured as virtual servers of multiple virtual servers; and an interface control component to select at least one virtual network interface of each of the one or more virtual servers along the pathway to operate in a polling mode, and to select a virtual network interface of at least one virtual server of the multiple virtual servers not along the pathway to operate in a non-polling mode.

Techniques for routing packets among virtual machines

Examples may include techniques to coordinate the sharing of resources among virtual elements, including service chains, supported by a shared pool of configurable computing resources based on relative priority among the virtual element and service chains. Information including indications of the performance of the service chains and also the relative priority of the service chains may be received. The resource allocation of portions of the shared pool of configurable computing resources supporting the service chains can be adjusted based on the received performance and priority information.

Techniques to dynamically allocate resources of configurable computing resources

Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination.

Dynamically entering low power states during active workloads

Methods and apparatus relating to adaptive interrupt coalescing for energy efficient mobile platforms are discussed herein. In one embodiment, one or more interrupts are buffered based on communication throughput. At least one of the one or more interrupts are released in response to expiration of an interrupt coalescing time period. Other embodiments are also claimed and described.

Adaptive interrupt coalescing for energy efficient mobile platforms

Growing community of inventors

Portland, OR, United States of America

Mesut A Ergin