Unisys Corporation

Merwin H Alferness

David R Johnson

Joseph P Kerzman

James R McBreen

Charles R Caldarale

Wayne D Ward

David C Johnson

Mark D Aubel

John Z Nguyen

Eric S Collins

John Steven Kuslak

Peter B Criswell

Hans Christian Mikkelsen

James Edward Rezek

Richard M Shelton

Francis A Stephens

Frederick H Hathaway

Mark A Vasquez

James W Douglas

Donna J Plunkett

A method and apparatus for selectively providing modularity and/or hierarchy to a behavioral description of a circuit design. This is accomplished by providing a template call in the behavioral description of the circuit design. The template call provides a reference to a corresponding template behavioral description. The behavioral description of the circuit design is expanded using an expander preprocessor, wherein a command line switch is used to selectively provide modularity and/or hierarchy to the resulting behavioral description.

Method and apparatus for providing modularity to a behavioral description of a circuit design

A method and apparatus for efficiently selecting cells within a circuit design database. The invention includes four primary features for selecting cells including (1) selecting only those cells that are in a pre-identified region and within a pre-identified selection area; (2) maneuvering through the circuit design hierarchy and selecting cells or regions at selected levels of hierarchy by using predetermined up and down hot-keys; (3) sorting selected cells by instance name, and manually selecting a desired cell or region from the resulting sorted list; and (4) sorting selected cells by a corresponding net name, and manually selecting a desired cell or region from the resulting sorted list.

Method and apparatus for selecting components within a circuit design database

A system and method for adding a queue entry containing message data to a queue shared by communicating, sequential processes includes an enqueue instruction. The enqueue instruction attaches a queue entry to either the tail or the head of the shared queue, as specified by an application programmer. Execution of the enqueue instruction includes blocking access to the queue by other processes, updating queue linkages, activating processes waiting on entries being made to the queue, monitoring interrupts, and validating the appropriate queue data structures. If desired, in lieu of adding a queue entry containing message data to the queue, the enqueue instruction inserts an event indicator into the shared queue structure, thereby providing synchronization capabilities between communicating processes.

Enqueue instruction in a system architecture for improved message passing and process synchronization

A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry which is visible in the virtual address space of the first process. The queue entry is added to a queue by the sending process directing the processor to execute an enqueue instruction. The receiving process removes the queue entry from the queue by directing the processor to execute a dequeue instruction. The receiving process then has direct access and visibility to the contents of the queue entry without having to copy the data into its virtual address space. Instead of sending data in a queue entry, a sending process may send an event indicator and no data. The receiving process may then wait on an empty queue until an event notification is received in a queue entry enqueued to the queue. Protection is provided by the system to prevent unauthorized access to the queue by other processes active in the system.

System architecture for improved message passing and process

A system and method for emulating a target system's hardware using highly parallel software emulation. Target system hardware under the control of program instructions is emulated using parallel software activity routines. Each of the program instructions is sequentially provided to a series of the activity routines, where each activity routine is a stage of a software emulation pipeline. Each activity routine emulates a particular function designated by the particular program instruction of the target system. The information is forwarded from each of the stages of the series of activity routines to their successive stages in the series. Each stage forwards its associated information to its respective successive stage when the stage has completed its designated activity, and has recognized that its respective successive stage has completed its respective function and is ready to accept more information.

Parallel emulation system and method

A system and method for providing high speed emulation of a computer system by transforming selected target instructions and bypassing target instruction decoding for those target instructions which have been transformed. A target computer system, controlled by a plurality of target instructions, is emulated on an emulation host computing system. Target instructions are successively loaded into the emulation host computing system in the order that the target instructions would be executed. The target instructions are decoded to identify the functions designated by the target instructions, and these functions are executed by the emulation host computing system. Emulation information is assigned to selected target instructions, where the emulation information controls execution of these selected target instructions, referred to as transformed instructions. Software routines identified by the emulation information are initiated for these transformed instructions, where the software routines execute the functions of the target instruction in the machine language of the emulation host computing system.

Selective emulation interpretation using transformed instructions

An Internet checksum for use by TCP/IP is generated in a single macro-instruction called a Block Add Octets instruction. Extraneous overhead of macro-instruction looping and bit masking is eliminated by combining checksum operations into a single macro-instruction using a block add approach. The programmer specifies the address in memory and the number of double-words of message data to be added together within a single instance of the Block Add Octets instruction so that looping and jump/branch instructions are not needed. The Block Add Octets instruction fetches all octets (8-bit data segments) contained in full double words from memory and adds them into the checksum. The method handles partial double words of data, full double words, and odd numbers of double words, whereby a double word consists of four octets. The checksum is calculated using one's complement arithmetic rather than two's complement, thereby increasing the speed of checksum calculation because the 'end around carry' is eliminated. The number of octets that can be added to the checksum per processor cycle is greatly increased, thereby significantly improving overall TCP/IP performance.

Method for generating an internet protocol suite checksum in a single

A base address prediction system for predicting one of a plurality of base addresses to be added to a known relative address in order to generate an absolute address. An actual base address determined from the relative address is also generated. The actual base address determination takes longer to generate than the predicted base address determination, and therefore the predicted base address is used to select a base address as long as the prediction is correct. Circuitry exists to compare the predicted base address with the actual base address, and if not equal, the predicted base address will be nullified, and the actual base address will be used. Prediction modes are dependent on whether the relative address indicates an instruction fetch or an operand fetch. Where the relative address indicates an instruction fetch, the prediction will be based on the last base address used, on the assumption that instructions will be contiguous in a single block of memory. Where the relative address indicates an operand fetch, the prediction will only change upon the occurrence of two consecutive incorrect predictions, and the actual base address will be used during incorrect prediction periods. Staged latching circuitry and comparison circuitry provides a method of determining whether two consecutive predictions were incorrect.

Address prediction for relative-to-absolute addressing

A system and method for removing a queue entry containing message data from a queue shared by communicating, sequential processes includes dequeue (DEQ) and dequeue or wait (DEQW) instructions. The dequeue instruction removes a queue entry from the head of the shared queue, thereby providing access to the message data contained in the queue entry to the dequeuing process. The dequeue or wait instruction removes a queue entry from the shared queue if there is one, otherwise it suspends the execution of the dequeuing process until an entry is enqueued to the queue. If an event is selected by the dequeuing process, the dequeuing process is suspended until notification of the event is detected in the shared queue. Execution of the dequeue and dequeue or wait instructions include blocking access to the queue by other processes, updating queue linkages, deactivating processes waiting on entries or events being made to the queue, monitoring interrupts, and validating the appropriate queue data structures.

Dequeue instruction in a system architecture for improved message

A digital instruction processor control system for an instruction processor having a multiple stage instruction execution pipeline capable of executing binary instructions in fixed predetermined stages. The control system includes a hardware controller to generate control signals for execution of all pipeline stages of standard instructions and for the first stage of extended cycle instructions and provides a main microcode controller to provide programmed control signals for controlling all subsequent stages of execution of extended cycle instructions. The control system also utilizes a separate sequence microcode controller for execution of certain instructions of a predetermined type including decimal instruction execution, during which time the main microcode controller is under control of the separate sequence controller.

Instruction processor control system using separate hardware and

A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry on the shared memory queue. Hierarchical queuing allows a sending process to collect multiple message segments as entries in a local sub-queue, which is enqueued as a single entity to the shared memory queue when all message segments are present. The receiving process dequeues the sub-queue in one operation, thereby increasing the efficiency of message transfer while preventing the erroneous dequeuing of message segments when multiple receiving processes are waiting on the same shared memory queue. In this manner, the logical maximum size of a message being passed between processes is expanded.

Hierarchical queuing in a system architecture for improved message

An apparatus for and method of loading the addressing environment of a large scale multiprogrammed instruction processor. The addressing environment is normally loaded upon initiation of an application program. Providing a separate addressing environment for each application program permits the software to be developed using virtual addressing. The addressing environment is loaded to permit the instruction processor to convert the virtual addresses to absolute addresses. The addressing environment is specified by a stack of base registers. These are loaded sequentially from a data store containing the virtual address of the initial location of each data bank to be accessed. The virtual addresses are converted to absolute addresses for loading into the base registers. During the loading process, each virtual address is evaluated to determine if it defines a valid data bank. If it does, the corresponding base register is loaded. If the virtual address is not valid, the effort to load the corresponding base register is saved and the next valid virtual address is loaded.

Method of and apparatus for rapidly loading addressing environment by

An apparatus for and method of loading the user addressing base register of a large scale multiprogrammed instruction processor. The base register is normally loaded to permit a user application program to access a different data segment. Providing a base register addressing environment for user application programs permits the software to be developed using virtual addressing. The addressing environment is specified by a stack of base registers. These are loaded from a data store specifying a virtual address for each data segment. During the loading process, an absolute address corresponding to the virtual address is loaded into each base register. To load a base register, a determination is made whether the future value differs from the previous value by a differential offset. If yes, the base register is loaded with an absolute address corresponding to the sum of the previous bank descriptor and the new offset. If no, the new base register value is computed by accessing a bank description table.

Method of and apparatus for rapidly loading addressing registers

An apparatus for and method of aborting the remainder of a microinstruction if a branch by that microinstruction or a subsequent microinstruction renders the results of said microinstruction to be invalid. Within an instruction processor having the capability for pipelined operation, the sensitivity of an operation of a microinstruction to the branch condition may be indicated by one or more abort bits. If an abort bit is set and the corresponding branch condition occurs, the remainder of the microinstruction is aborted. By thus indicating the sensitivity to a branch, the microinstruction can proceed under full pipeline operation until such time as a branch condition actually occurs.

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New Brighton, MN, United States of America

Merwin H Alferness