International Business Machines Corporation

Mervyn Yee-Min Tan

Robert J Allen

Evanthia Papadopoulou

Jason D Hibbeler

Michael S Gray

Robert F Walker

Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.

Critical area computation of composite fault mechanisms using Voronoi diagrams

A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.

Integrated circuit yield enhancement using Voronoi diagrams

Critical area computation of composite fault mechanisms using voronoi diagrams

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South Burlington, VT, United States of America

Mervyn Yee-Min Tan