International Business Machines Corporation

Mervyn Y Tan

Robert J Allen

Evanthia Papadopoulou

Jason D Hibbeler

Daniel Nelson Maynard

Robert F Walker

Sarah C Braasch

Albert Manhee Chu

Michael S Gray

Faye D Baker

Ruchir Puri

Kevin W McCullen

Hua Xiang

Louise Helen Trevillyan

Matthew Thomas Guzowski

Sarah C Prue

Peter K Chan

Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

IC layout optimization to improve yield

A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.

Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design

An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.

System and method for global circuit routing incorporating estimation of critical area estimate metrics

In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.

Method and apparatus for net-aware critical area extraction

In embodiments of a method critical area is calculated based on both independent and dependent compound fault mechanisms. Specifically, critical area is calculated by generating, for each simple fault mechanism in the compound fault mechanism, a map made up of polygonal regions, where values on a third dimensional z-axis represent the critical defect size for each single fault mechanism at a point x,y. These maps are overlaid and the planar faces (i.e., top surfaces) of each region of each map are projected onto the x,y plane in order to identify intersecting sub-regions. The dominant fault mechanism within each sub-region is identified based on an answer to predetermined Boolean expression and the critical areas for all of the sub-regions are accumulated in order to obtain the total critical area for the compound fault mechanism.

Method for computing the critical area of compound fault mechanisms

A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.

Sample probability of fault function determination using critical defect size map

Probability of fault function determination using critical defect size map

Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.

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South Burlington, VT, United States of America

Mervyn Y Tan