Sperry Corporation

Merlin L Hanson

Robert E Swenson

Garold S Tjaden

Barry R Borgerson

James R Hamstra

Anthony R Talarczyk

Arnold R Schmalzbauer

Larry J Kelson

In a cache/disk sybsystem employing the post-store technique, each file is assigned a file number. The file number is an address in a directory on a disk, this address containing pointers to the physical disk space assigned to that file. During normal operation of the subsystem a device number and address are utilized to transfer written-to segments of data from a cache store to a disk. If a failure occurs which prevents the cache-to-disk transfer of a segment of data, a storage control unit forms a status word and a sense message. The sense message includes the file number and information defining the fault. A host processor is then notified that the status word is available. The host processor obtains the status word and indexes into a status action branch table. The branch table entry directs the host processor to issue a Sense I/O command to obtain from the storage control unit the sense message identifying the fault. The executive program of the host processor may subsequently utilize the sense message, which also includes the file number, to assign new disk space at which the segment of data may be recorded. The segment of data which could not be written to the disk is first read into the host processor. The host processor then issues a command to write the segment of data into the newly assigned disk space.

Cache/disk subsystem with file number for recovery of cached data

In a hierarchical memory system, replacement of segments in a cache memory is governed by a least recently used algorithm, while trickling of segments from the cache memory to the bulk memory is governed by the age since first write. The host processor passes an AGEOLD parameter to the memory subsystem and this parameter regulates the trickling of segments. Unless the memory system is idle (no I/O activity), no trickling takes place until the age of the oldest written-to segment is at least as great as AGEOLD. A command is generated for each segment to be trickled and the priority of execution assigned to such commands is variable and determined by the relationship of AGEOLD to the oldest age since first write of any of the segments. If the subsystem receives no command from the host processor for a predetermined interval, AGEOLD is ignored and any written-to segment becomes a candidate for trickling.

Hierarchical memory system with variable regulation and priority of

In a data processing system having a host processor, a cache store for storing segments of data, a bulk memory and a storage control unit for controlling transfers between the processor, cache store and bulk memory, the storage control unit normally responds to a read or write command from the host processor to control the transfer of data. If a copy of the data transferred is not resident in the cache store then a copy is written therein by the storage control unit. If the length of a data transfer exceeds a first threshold length then the storage control unit does not write a copy of the data into the cache store. If the length of a data transfer exceeds a second threshold length, and the transfer begins on a segment boundary and comprises an integral number of segments, then the storage control unit does not write a copy of the data into the cache store. The writing into the cache store is transparent to the host processor. The use of a transfer threshold prevents data from being entered into the cache store when it is not likely to be used again soon. Two thresholds are provided because the data transferred in long transfers of an integral number of segments is even less likely to be used again soon than the data transferred in long transfers that do not begin on a segment boundary or comprise an integral number of segments.

Cache/disk subsystem with cache bypass

A cache/disk subsystem includes a host processor, a cache store, a disk drive device for driving a disk, and a storage control unit for controlling the transfer of data between the host, disk and cache store. The cache store holds segments of data which have been read from, or are to be written to, the disk. When the host issues a normal WRITE command to the storage control unit and none or a part only of the data from the disk space specified by the command is resident in the cache store, the segment or segments of data in the disk space are staged into the cache store and overlayed with data from the host. A directory in the host keeps track of the disk segments previously written to. When the host is ready to issue a WRITE command it checks the directory and, if the segment or segments to be written to have not previously been written to, then the host issues an ACQUIRE WRITE command. The storage control unit includes controls responsive to an ACQUIRE WRITE command for bypassing the staging operation. The storage control unit also includes circuits for converting a normal WRITE command to an ACQUIRE WRITE command when the beginning and ending addresses of a normal WRITE command fall on segment boundaries. The ACQUIRE WRITE command eliminates unnecessary staging from the disk to the cache store in situations where there is no data to be staged or all of the data which would be staged would be overwritten.

Cache/disk subsystem with acquire write command

Decision and control logic for use in digital computers that operate in cycles provides binary valued decision signals for effecting decisional control within the computer such as that utilized in conditional branching. The decision signals are provided in accordance with binary valued control functions of binary valued static and dynamic control variables utilized in the computer. The dynamic control variables are available in a computer cycle subsequent to the availability of the static variables and represent conditions of various components of the computer. Truth tables of the control functions are stored in logic function memories addressed by logic function selection control fields of computer control words, the control fields selectively addressing the truth tables in accordance with the desired functions. The static variables are utilized for addressing the logic function memories for providing the truth table entries corresponding to the selected function of the static control variables and the dynamic variables select among the addressed truth table entries to provide the binary valued decision control signals. Preferably the logic function memories are implemented by LSI integrated circuits.

Table driven decision and control logic for digital computers

A computer which is configured to perform its operations in overlapped fashion. During each computer cycle the next instruction is fetched, the function designated by the previous instruction is executed, and values are stored that were computed with respect to the instruction previous to the one being executed. Thus a three-way overlap is effected. To minimize time penalties due to conditional branches and jumps, each instruction word includes two next instruction address fields, two function fields and two deferred action fields. The computer includes decision logic for providing binary decision signals for conditionally selecting one of the fields from each of the next address fields, the function fields and the deferred action fields thereby conditionally fetching the next instruction, conditionally selecting the function to be performed and conditionally storing values during the same cycle in accordance with the decision signals. Thus the computer has the capability of performing conditional branches each cycle, in an unbroken rhythm.

Digital computer with overlapped operation utilizing conditional control

A microprogrammable CPU for a computer utilizes an architecture wherein macro instructions of the computer repertoire are executed by micro instruction routines stored in a control store memory. The micro instruction routines are comprised of micro instruction words for controlling the micro operations to be performed in executing the macro instructions. The CPU includes a plurality of local processors each configured to perform a plurality of the micro operations. A macro instruction fetched into the macro instruction register of the computer addresses the corresponding micro instruction routine in the control store memory and the plurality of local processors operate concurrently to simultaneously perform the micro instructions of the routine on behalf of the fetched macro instruction. Thus a stream of macro instructions flowing through the macro instruction register is decomposed into a plurality of concurrently executed micro instruction streams flowing through the respective local processors. Preferably the local processors are constructed utilizing micro processor LSI integrated circuits. Each local processor is operated in an overlapped mode with respect to micro instruction fetching, execution and storage of results. Each local processor has real and phantom branching capabilities provided by plural next address fields and plural function control fields in the micro instruction words. Decision points provided in the computer select between the next address fields and select between the function control fields to perform the real and phantom branching respectively. The decision points are provided by control logic driven by tables storing functions of plural variables where functions and variables are selectable by the micro instruction words.

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Arden Hills, MN, United States of America

Merlin L Hanson