International Business Machines Corporation

Merle E Houdek

Frank G Soltis

Roy L Hoffman

Glen R Mitchell

Eugene R Jones

David Otto Lewis

Larry Wayne Loen

Charles Porter Geer

William G Kempke

James Gregory Ranweiler

Thomas M Walker

Lam Q Dang

John A Soyring

Storage addressing error detection circuitry detects addressing errors in a computer system during data transfers between an I/O unit and main storage where main storage has logical boundaries which if crossed can cause destruction of data. The central processing unit (CPU) of the computer system furnishes the I/O unit the starting address for the data transfer and thereafter the I/O unit furnishes addresses for completion of the data transfer. The starting address contains a hash value related to the logical boundaries. Each time the I/O unit presents an address with a hash value for a data transfer another hash value is generated from the remainder of the address passed by the I/O unit. If the two hash values do not compare equal, a logical boundary in main storage would be crossed and to prevent such an occurrence the storage operation is inhibited and an error signal is sent to the I/O unit which then terminates the data transfer. A write to a read only storage area is also detected as a storage addressing error. A write hash is a read hash inverted. The read hash would not compare equal to the write hash and an error signal would be generated and sent to the I/O unit if the I/O unit were attempting to write into a read only storage area.

Storage addressing error detection circuitry

Storage serialization apparatus in a multiprocessor computer system enables multiple processors to concurrently execute instructions which access storage without materially affecting performance by keeping the amount of storage locked to a minimum, i.e., a page. The duration of serialization need be only for one instruction execution time and only instruction operands need be accommodated for serialization. Each storage request is intercepted by an associative register stack where there are two registers for each operand, one of the two being for operand page crossings. After a processor has locked access to an area of storage, execution of the instruction begins and all other processor are locked out but only with respect to that locked area. Other processors can access other storage areas during the instruction cycle. When the execution of the instruction completes, the processor releases the locked area of storage by invalidating the entries in its associative register array. A mechanism arbitrates and breaks possible deadlocks.

Multiprocessor storage serialization apparatus

Apparatus for compressing and buffering large amounts of data, transferring the buffered data to a slower speed storage device and controlling the stopping and starting of the central processing unit (CPU) is provided for a virtual storage computer system where the data is collected in real time; the data being collected are all storage addresses to facilitate address tracing. Each real main storage address is collected to the external interface between the central processing unit (CPU) and main storage and converted to a virtual address. The virtual address is compressed and entered into a large buffer via buffer control logic. The buffer control logic sends a signal to stop the CPU when the buffer becomes full and restarts it at the exact point it had stopped after the buffer has been emptied by the transfer of data from it to a slower speed storage device.

Apparatus for compressing and buffering data

Task dispatching for an asymmetric or symmetric multiprocessor system is provided where all the processors are dispatched from a single task dispatching queue. The workload, i.e. tasks, of the multiprocessor system is distributed to the available processors. Each processor includes a task dispatcher and a signal dispatcher. The signal dispatcher runs in a processor whenever a task dispatching element (TDE) is put on the task dispatching queue (TDQ) as a result of the task running in the processor. The signal dispatcher examines the TDEs enqueued on the TDQ and determines if any task dispatcher should be invoked, i.e. if any processor is running a lower priority task a task switch should occur. If so, it signals the selected processor to invoke its task dispatcher. After completing the task switch, the selected processor must invoke its signal dispatcher to determine if the task it had been performing should now be performed on some other processor in the multiprocessor system.

Multi-processor task dispatching apparatus

Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set the corresponding tag bits OFF. Thus, if a pointer was modified inadvertently by one of these data handling instructions, the fact that the pointer is untagged is detected and the values in the pointer are treated as invalid when the pointer is used by the Load and Verify Tags instruction. Instructions to load, store, set, move, extract and insert tags are implemented by the tagged pointer handling apparatus. A Load and Verify Tags instruction checks the validity of the pointer and if valid, loads the pointer into a specified general purpose register. A Store and Set Tags instruction stores the value in a specified general purpose register into main storage and sets the associated tag bits ON. A Move and Set Tags instruction moves a word from one location in main storage to another or the same location in main storage and sets the associated tag bits ON. A Move Characters and Tags instruction moves a word and the associated tag bits from one storage location to another storage location. An Extract Tags instruction fetches each word from an operand in main storage, extracts the tag bits, compresses the tag bits to one tag bit per quadword, and stores the tag bits in main storage as data. An Insert Tags instruction fetches the tag bits stored in main storage as data, expands the tag bits to one tag bit per word, and inserts them on each associated word of an operand in main storage.

Tagged pointer handling apparatus

The present invention discloses an apparatus for the efficient translation of virtual addresses to main storage addresses by means of a hash index table which contains main storage addresses. Hash generator apparatus is provided for generating a uniform distribution of hash index table entry addresses from a non-uniform distribution of virtual addresses in a data processing system, where the size of the hash index table is variable and is based on the size of main storage. A field of bits within the virtual address corresponding to the page identification bits are reversed in order and aligned with two groups of bits from a field of bits within the virtual address corresponding to object identification bits, and the three groups of bits are applied to an EXCLUSIVE-OR circuit. The alignment of the three groups of bits and the size of the hash index table entry addresses generated by the present invention are based on the size of the hash index table.

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Rochester, MN, United States of America

Merle E Houdek