International Business Machines Corporation

Merle E Homan

Guenther Keith Machol

George Radin

Jon L Cross

Dale E Fisk

Robert L Griffith

Waldo J Richards

Richard La Malm

Larry Eugene Svelund

Larry M Warren

Accelerated instruction mapping external to source and target

A microprocessor external instruction feature which provides for a single chip microprocessor with on-chip read only instruction store (ROS) that can also be operated with an off-chip instruction store. To accomplish this, the microprocessor instruction sequencing logic (instruction store, instruction register, instruction counter, and sequencing logic) is duplicated off-chip. An XI MODE input pin signal causes the microprocessor to take its instructions from the external instruction store via 12 XI input pins instead of from the on-chip ROS. A BR DECISION output pin signal from the microprocessor, which indicates that the branch conditions have been met, causes the external instruction counter to be loaded with a branch address from the external instruction register instead of being stepped by external sequencing logic. A WAIT output pin signal causes the external instruction feature logic to suspend operations while the microprocessor is in its wait state.

Single chip microcomputer selectively operable in response to

Apparatus under microprocessor control for use in communicating over a serial communication loop with a remote attached control unit. It is capable of establishing frame synchronization, interpreting commands, assembling data and transmitting bits on the loop. The apparatus also communicates with I/O devices over a demand/response interface. A microprocessor interface with the loop includes loop sync control which establishes bit synchronization and generates a restart pulse at bit receive time and bit send time. The execution of instructions by the microprocessor is stopped and the microprocessor enters a wait state when it has finished all previous work and is ready to receive a loop bit. When it is time to receive the loop bit the microprocessor is restarted in response to the restart pulse from the loop synchronization control. For output operations to a device, the microprocessor loads the device address and a device command or data into shift registers and initiates the transfer by setting a latch. When the transfer to the device is completed, this latch is reset in response to a signal from the device.

Apparatus for control and data transfer between a serial data

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Los Gatos, CA, United States of America

Merle E Homan