Texas Instruments Corporation

Mercer Brugler

Freidoon Mehrad

Brian Keith Kirkpatrick

Rajesh B Khamankar

Eddie Hearl Breashears

Ju-Ai Ruan

Jon Holt

Cameron Gross

Steven P Zuhoski

Jie Xia

Sarah Hartwig

Glenn J Tessmer

Edward L Mickler

Corbett Zabierek

The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy sourceto improve the physical property defect value.

Method for improving a physical property defect value of a gate dielectric

The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate having an oxidized region, and establishing a first loading position in a first process chamber. The first and second substrates are consecutively inserted into the first process chamber and generally simultaneously processed, wherein the oxidized region is reduced by exposure to a first plasma. The first and second substrates are then consecutively removed and the first substrate is inserted into a second process chamber and subsequently processed. The second substrate is then inserted into the second process chamber and the first and second substrates are simultaneously processed. The first substrate is the removed, and the second substrate is processed again. According to one exemplary aspect, the first and second substrates are exposed to a first temperature in the first process chamber for approximately half the time the first and second substrates are exposed to a higher second temperature in the second process chamber while maintaining throughput of substrates.

Method for reducing contamination, copper reduction, and depositing a dielectric layer on a semiconductor device

A method for fabricating a non-FLASH integrated circuit that minimizes Vmin shift. A protective overcoat ( ) is deposited to protect and encapsulate the top metal interconnect layer ( ). The protective overcoat ( ) is patterned and etched to form bondpad windows either before or after depositing the final metal interconnect layer ( ). A sinter that is normally performed after forming the bondpad windows is either omitted or the temperature of the sinter is kept at or below 350&deg; C.

Control of Vmin transient voltage drift by maintaining a temperature less than or equal to 350&deg; C. after the protective overcoat level

A method of forming a semiconductor component having a conductive line ( ) and a silicide region ( ) that crosses a trench ( ). The method involves forming nitride sidewalls ( ) to protect the stack during the silicidation process.

Sidewall process for forming a low resistance source line

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Mercer Brugler