Hewlett-packard Company

Avago Technologies General IP (singapore) Pte. Ltd.

Agilent Technologies, Inc.

Pixart Imaging Incorporated

Other

Mercedes E Gil

John G Rohrbaugh

Michael J Bennett

Thomas H Baker

Robert W Proulx

Norman C Chou

Edmundo Rojas

Richard L Schober, Jr

Ian G Colloff

S Paul Tucker

Yolin Lih

Sarangan Narasimhan

Jerome D Wong

Zhi Zhong Huang

Xu Zhang

Zhang Xiaoyang

Xiao Yan Zheng

A test system for testing a capacitive-sense touchscreen is disclosed. Specifically, the test system may be incorporated within a controller that is also used to control operations of the touchscreen. The controller may include an Integrated Circuit and the test system may correspond to a test capacitor embedded into the Integrated Circuit.

In-situ detection of touchscreen panel shorts

Various embodiments of a low-power-consumption analog-to-digital converter ('ADC') for a touchscreen or touch panel in a capacitive sensing system are disclosed. The ADC is configured to operate in a first mode or a second mode. The first mode is characterized by a first resolution having a first number of ADC bits and a first level of power consumption associated therewith. The second mode is characterized by a second resolution having a second number of bits and a second level of power consumption associated therewith. The ADC operates under control of the controller and is configured such that the first number of bits is greater than the second number of bits and the first power level is greater than the second power level. The controller causes the ADC to switch from operating in the first mode to operating in the second mode when low radio frequency (RF) noise conditions are detected by sense circuitry, the ADC and/or the controller.

Controller and ADC for low power operation of touchscreen device

A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory. The packet transfer request generator initiates a transfer request over a switch with a remote destination. While the request is processed, the packet checker verifies packet correctness and stores the packet data for transmission to the remote destination. If a packet is in error, a bad tag is set and the packet transfer is aborted.

Handling and discarding packets in a switching subnetwork

In general, a system and method for providing data packet flow control is disclosed. Generally, a switch is provided that contains a series of ports, an arbiter and a hub. The arbiter determines an outgoing port, wherein the outgoing port is one port for the series of ports, for transmission of a data packet received by the switch, determines whether the outgoing port is available to receive the received data packet, and regulates transmission of the received data packet to a destination end node. The hub provides a point-to-point connection between any two of the series of ports and the arbiter.

Systems and methods for providing data packet flow control

A networking system includes a plurality of ports, each adapted to send and receive data. A switch core has a first channel configured to receive a logical input flow from each of the plurality of input ports, and has a second channel configured to receive a raw input flow from each of the plurality of input ports. Each logical input flow is carried by its corresponding raw input flow. A plurality of port mirrors are selectable from the plurality of ports. Each of the plurality of port mirrors is configured to produce a duplicate copy of at least one of the logical input flow and the raw input flow available at a selected port.

Method and apparatus for input/output port mirroring for networking system bring-up and debug

A fast with-in range comparator is implemented in digital logic. A packet arrives at a device for processing. Initial packet data that is available in a first read cycle, is used to compute data that is necessary for later cycles. The initial data and the subsequently data are then used to test a single value against a range of values. In a method of the present invention a range is separated into two ranges. An upper limit of the first range is tested to determine whether the value is below the upper limit. If this test fails, the value is tested to determine whether the value is between the upper limit of the first range and the upper limit of the full range. The ranges are tested by constructing a bit vector. Data representing the capability of a communicating port, is then used to index into the bit vector. The outcome of the index is a value that signifies whether the port can support the packet or not.

Method and apparatus for fast integer within-range compare

A method and system to arbitrate between a plurality of resource requests are disclosed. In each arbitration within a current round of arbitration, a winning request is identified based on a priority associated with each requester participating in the arbitration and a set of values stored in a mask register. In response to identifying the winning request, a mask register value corresponding to a requestor of the winning request is updated to disqualify this requestor from further participation in the current round of arbitration. When the current round of arbitration completes, the set of values in the mask register is reset to allow each requestor to participate in the next round of arbitration. The current round of arbitration begins when each requester is qualified to participate in the current round of arbitration and completes when every participating requestor has been disqualified.

Mask-based round robin arbitration

An input port is described having an input policing unit that checks if a virtual lane has a sufficient number of credits to carry an input packet received by the input policing unit. The input port also has a request manager that generates a request for the packet to be switched by a switching core. The input port also has a packet Rx unit that stores the packet into a memory by writing blocks of data into the memory. The input port also has a packet Tx unit that receives a grant in response to the request and reads the packet from the memory in response to the grant by reading the blocks of data. The input port also has a pointer RAM manager that provides addresses for free blocks of data to said packet Rx unit and receives addresses of freed blocks of data from said packet Tx unit.

Apparatus and methodology for an input port of a switch that supports cut-through operation within the switch

An architecture and method for dynamically allocating and deallocating memory for variable length packets with a variable number of virtual lanes in an Infiniband subnetwork. This architecture uses linked lists and tags to handle the variable number of Virtual Lanes and the variable packet sizes. The memory allocation scheme is independent of Virtual Lane allocation and the maximum Virtual Lane depth. The disclosed architecture is also able to process Infiniband packet data comprising variable packet lengths, a fixed memory allocation size, and deallocation of memory when packets are either multicast or unicast. The memory allocation scheme uses linked lists to perform memory allocation and deallocation, while tags are used to track Infiniband subnetwork and switch-specific issues. Memory allocation and deallocation is performed using several data and pointer tables. These tables store packet data information, packet buffer address information, and pointer data and point addresses. The tags allow the memory allocation and deallocation process to correctly handle good and bad packets, as well as successive blocks within a data packet.

Buffer management architecture and method for an infiniband subnetwork

A method and system to arbitrate requests of a plurality of ports of an interconnect device are provided. Every port receives combined pending request data that includes a pending request indicator associated with each of the plurality of ports. Each pending request indicator specifies whether a corresponding port has a pending request that needs to be submitted to a request bus of the interconnect device. Further, at each port, a turn to submit a request to the request bus is allocated to one of the plurality of ports based on the combined pending request data, a set of values stored in a mask register and a priority scheme associated with the plurality of ports.

Request bus arbitration

The present invention is a method for accessing a user defined custom routine through a graphical interface of an application program. The method comprises the steps of: (a) linking the user defined custom routine to the application program; (b) displaying a means for accessing the user defined custom routine on a graphical interface; and (c) transferring control to the user defined custom routine when a user activates the means.

Apparatus and method for mapping a custom routine to an interface button

A system comprises a flag interface module, a flag query having a selectable value based on a user authorization level, a query communicator, and a flag value communicator for communicating a new flag value from the flag interface module to a test program in response to the query communicator that enables a user to modify an execution sequence [e.g., modifying the flow] of the test program executing on a computer controlling a testing system. The execution sequence of the test program is modified only if the user has a proper authorization level. The execution sequence is modified by an authorized user without requiring the test program to be recompiled.

Apparatus and method for changing the behavior of a computer program

The present invention is a method for specifying test flow and binning of an integrated circuit part in an integrated circuit tester. The method comprises the steps of receiving descriptions of the tests, receiving test flow statements indicating when the tests are to be executed, receiving binning statements, executing the tests as indicated by the test flow statements, and binning the IC device as indicated by the results of the tests.

Apparatus and method for specifying the flow of test execution and the

The invention is a method for displaying wafer test results from an integrated circuit tester in real time. The method comprising the steps of: (a) receiving wafer dimensions and die dimensions from a wafer handler; (b) creating a template representative of a wafer having cells representative of a die from the wafer dimensions and the die dimensions; (c) displaying the template; (d) invoking a tester to test a selected die of a selected wafer; (e) receiving test results from the tester; (f) displaying the test results on a selected cell which corresponds to the selected die; and (g) repeating steps (d)-(f) as required.

Growing community of inventors

Fort Collins, CO, United States of America

Mercedes E Gil