Changxin Memory Technologies, Inc.

Beijing Superstring Academy of Memory Technology

Mengkang Yu

Xingsong Su

Weiping Bai

Lianhong Wang

Guangsu Shao

Zhen Zhou

A preparation method for the capacitor structure includes: forming a dielectric layer on a first electrode, wherein, the dielectric layer includes a first amorphous layer and a high dielectric constant layer which are stacked, the first amorphous layer maintaining an amorphous structure after annealing, and the high dielectric constant layer being formed by crystallizing an initial dielectric constant layer after annealing; and forming a second electrode on the dielectric layer. Since the first amorphous layer remains an amorphous structure after annealing, electron transport can be suppressed, thereby reducing the leakage current of the capacitor structure.

Preparation method for capacitor structure, capacitor structure, and memory

The present disclosure provides a capacitor and a manufacturing method thereof, and a semiconductor device. The capacitor includes a plurality of bottom electrodes, a top electrode structure, a dielectric layer, and a gap filling layer, where the top electrode structure is formed on one side of each of the plurality of bottom electrodes, one side of the dielectric layer is in contact with the plurality of bottom electrodes and the other side is in contact with the top electrode structure, and the gap filling layer fills remaining gaps between the plurality of bottom electrodes.

Capacitor and manufacturing method thereof, and semiconductor device

The application relates to an electrode layer, a capacitor and methods for electrode layer and capacitor manufacture. The method for electrode layer manufacture comprises the following steps: forming a first electrode layer, the first electrode layer comprising a doped Titanium Nitride (TiN) layer; and forming a second electrode layer on the surface of the first electrode layer, the second electrode layer comprising a TiN layer or a work function layer.

Electrode layer, capacitor and methods for electrode layer and capacitor manufacture

A capacitor structure includes two electrodes arranged oppositely and a dielectric layer located between the two electrodes, wherein the dielectric layer includes at least two perovskite layers stacked; an amorphous layer is provided between every two adjacent perovskite layers; two outermost perovskite layers of the at least two perovskite layers are in contact with the two electrodes, respectively.

Manufacturing method for capacitor structure, capacitor structure and memory

A method for forming a capacitor, the capacitor and a semiconductor device are provided. The method includes: providing a semiconductor structure including a substrate, a stacked-layer structure, a protective layer, a first mask layer, and a photolithography layer which is provided with a plurality of cross-shaped patterns arranged in a square close-packed manner; patterning the first mask layer based on the photolithography layer; forming a plurality of through holes penetrating through the protective layer and the stacked-layer structure based on the patterned first mask layer by etching, in which in a direction perpendicular to a surface of the substrate, a projection of each through hole is cross-shaped, and the plurality of through holes are arranged in the square close-packed manner; and forming a first electrode layer, a dielectric layer and a second electrode layer covering an inner wall of each through hole to form the capacitor.

Method for forming capacitor, capacitor and semiconductor device

A manufacturing method for capacitor structure includes: forming a dielectric layer on a first electrode, wherein the dielectric layer includes metal oxide layers doped with preset oxides, and part of the preset oxide and a metal oxide share oxygen atoms; and forming a second electrode on the dielectric layer, wherein the first electrode, the dielectric layer and the second electrode constitute a capacitor structure.

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Hefei, China

Mengkang Yu