Altera Corporation

Xilinx, Inc.

Mengchi Liu

Weiqi Ding

Sergey Yuryevich Shumarayev

Wilson Wong

Cheng Hsiang Hsieh

Thungoc M Tran

Yu Xu

Mingde Pan

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

High-speed serial data signal receiver circuitry

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters ('DACs'). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).

Equalizer circuitry with selectable tap positions and coefficients

A clock data recovery module and a method of operation thereof are described. In an embodiment, a data stream is received. Transitions in the data stream are detected to provide phase signaling for indicating phase relationships to the transitions detected. A lock detector receives the phase signaling. The lock detector accumulates phase information from the phase signaling and temporarily stores an accumulated total of the phase information representative of a code change, and the lock detector determines whether the code change is within a set range over a time period and resets the accumulated total at a conclusion of the time period.

Clock data recovery using phase accumulation over a time period defined by a number of cycles of a clock signal

A phase interpolator is described. The phase interpolator can have a code-to-bias converter, and a phase interpolation interface. In an embodiment of a code-to-bias converter, a single digital-to-analog converter is provided to generate bias signaling associated with phase signals. A bleeder current source is provided to generate a bleeder current, where the bleeder current is selected responsive to phase so the phase signals do not reach zero current.

Phase interpolator

A voltage-controlled oscillator operates at high frequency without high gain by dividing the frequency range into a plurality of subranges, which preferably are substantially equal in size. Within any subrange, the full extent of variation in the control signal changes the frequency only by the extent of the subrange. The gain is thus substantially equal to the gain one would expect for the full frequency range, divided by the number of subranges. The subrange may be selected manually, or by an initial calibration process. In one embodiment, the oscillator includes a voltage-to-current converter and a current-controlled oscillator, with a current mirror arrangement. In that embodiment, selection of the subrange may be controlled by turning on the correct number of current legs.

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Fremont, CA, United States of America

Mengchi Liu