Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Mengcheng Lu

Jack T Kavalieros

Nazila Haratipour

Gilbert W Dewey

Matthew V Metz

Ian A Young

Seung Hoon Sung

Uygar E Avci

Chia-Ching Lin

Ashish Verma Penumatcha

Siddharth Chouksey

Sou-Chi Chang

Owen Y Loh

Jitendra Kumar Jha

Anand S Murthy

Glenn A Glass

Oleg Golonzka

Christopher J Wiegand

Scott Bruce Clendenning

Arnab Sen Gupta

Ryan Keech

Md Tofizur Rahman

Koustav Ganguly

Anant H Jahagirdar

Eric Charles Mattson

Uygar Avci

Owen Loh

Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

Low resistance approaches for fabricating contacts and the resulting structures

Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

Halogen treatment for NMOS contact resistance improvement

A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

MFM capacitor and process for forming such

A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

MFM capacitor with multilayered oxides and metals and processes for forming such

Embodiments of the present disclosure describe techniques and configurations associated with modulation of magnetic properties through implantation. In one embodiment, a method includes providing a substrate having an integrated circuit (IC) structure disposed on the substrate, the IC structure including a magnetizable material, implanting at least a portion of the magnetizable material with a dopant and magnetizing the magnetizable material, wherein said magnetizing is inhibited in the implanted portion of the magnetizable material. Other embodiments may be described and/or claimed.

Modulation of magnetic properties through implantation and associated structures

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Portland, OR, United States of America

Mengcheng Lu