Taiwan Semiconductor Manufacturing Comp. Ltd.

Meng-Yueh Liu

Chun Hsiung Tsai

Wei-Ken Lin

Chia-Ling Chan

Chien-Chang Su

Yi-Fang Pai

Yuh-Da Fan

Yuan-feng Chao

Kun-Hsiang Liao

Tzu-Chun Tseng

In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.

Semiconductor device and method

A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.

Cyclic epitaxial deposition and etch processes

The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing material without using GeHin an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.

Epitaxial formation mechanisms of source and drain regions

The embodiments of mechanisms for monitoring thermal budget of an etch process of a cyclic deposition/etch (CDE) process to form an epitaxially grown silicon-containing material are descried to enable and to improve process control of the material formation. The monitoring is achieved by measuring the temperature of each processed wafer as a function of process time to calculate the accumulated thermal budget (ATB) of the wafer and to compare the ATB with a reference ATB (or optimal accumulated thermal budget, OATB) to see if the processed wafer is within an acceptable range (or tolerance). The results are used to determine whether to pass the processed wafer or to reject the processed wafer.

The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.

Asymmetric cyclic desposition etch epitaxy

The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) descried enable forming an epitaxially grown silicon-containing material without using GeHin an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.

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Taoyuan, Taiwan

Meng-Yueh Liu