Taiwan Semiconductor Manufacturing Comp. Ltd.

Meng-Xiang Lee

Chung-Hsing Wang

Kuo-Nan Yang

Chin-Shen Lin

Wan-Yu Lo

King-Ho Tam

Li-Chung Hsu

Hao-Tien Kan

Ming-Hsien Lin

Ho Che Yu

Shih-Hsien Yang

Sheng-Hsiung Chen

Chun-Chen Chen

Hiranmay Biswas

Shao-huan Wang

Jhih-Hong Ye

Ren-Zheng Liao

Chung-Min Fu

Chi-Yeh Yu

Chung-hsing Wang

Jerry Kao

An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

Systems and methods for integrated circuit layout

Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Layouts for conductive layers in integrated circuits

The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.

Routing structure

Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.

Method for analyzing electromigration (EM) in integrated circuit

The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.

Routing structure and method of forming the same

Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.

A method for forming an integrated device includes following operations. It is provided a first circuit having a first connecting path in a metal line layer, a second connecting path, and a third connecting path. The second connecting path is electrically connected to a first connecting portion of the first connecting path in the metal line layer. The third connecting path is electrically coupled to a second connecting portion of the first connecting path in the metal line layer. An electromigration (EM) data of the first connecting path is analyzed to determine if a third connecting portion in the metal line layer between the first connecting portion and the second connecting portion induces EM phenomenon. The first circuit is modified to generate a second circuit when the third connecting portion induces EM phenomenon. The integrated device is generated according to the second circuit.

Integrated device and method of forming the same

Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to the current simulation result of the IC. It is determined whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout. The vias are in contact with the metal segment.

A system for simulating reliability of a circuit design includes: a first memory device, arranged to store a technology file, wherein the circuit design comprises a plurality of circuit cells, and the first memory device further stores a plurality of first failure rates corresponding to a first circuit cell in the plurality of circuit cells; a first simulating device, coupled to the first memory device, for generating a first specific failure rate of the first circuit cell according to the plurality of first failure rates and the technology file; and an operating device, coupled to the first simulating device, for generating a total failure rate of the circuit design according to the first specific failure rate.

System and method for simulating reliability of circuit design

A method for forming an integrated device includes following operations. A first circuit is provided. The first circuit has a first connecting path, a plurality of second connecting paths, and a third connecting path. The plurality of second connecting paths are electrically connected to a first connecting portion of the first connecting path. The third connecting path is electrically coupled to a second connecting portion of the first connecting path. An electromigration (EM) data of the first connecting path is analyzed to determine if a third connecting portion between the first connecting portion and the second connecting portion induces EM phenomenon. The first circuit is modified for generating a second circuit when the third connecting portion induces EM phenomenon. The integrated device according to the second circuit is generated.

A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identifying an RC network in the RC netlist; determining a characterization matrix corresponding to the RC network; updating the RC netlist by replacing the RC network with the characterization matrix; and calculating voltages and currents of the plurality of circuit nodes based on the updated RC netlist.

Method, system, and storage medium for RC extraction using hierarchical modeling architecture

A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identities a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Layout modification method and system

A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.

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Yunlin County, Taiwan

Meng-Xiang Lee