Taiwan Semiconductor Manufacturing Comp. Ltd.

Meng Wei Chen

Kuei Shun Chen

Chia-Chu Liu

George Liu

A method of patterning a semiconductor device including dividing a layout into more than one pattern. The method further includes depositing a film stack on a semiconductor substrate, depositing a hard mask on the film stack, and depositing a first photoresist on the hard mask. The method further includes patterning the first photoresist using a first pattern of the more than one pattern. The method further includes etching the hard mask to transfer a design of the first pattern of the more than one pattern to the hard mask. The method further includes depositing a second photoresist over the etched hard mask and patterning the second photoresist using a second pattern of the more than one pattern. The method further includes etching portions of the film stack exposed by a combination of the etched hard mask and the second photoresist.

Method of patterning a semiconductor device

The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.

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Taichung, Taiwan

Meng Wei Chen