Micron Technology Incorporated

Shanghai Tianma Micro-electronics Co., Ltd.

Meng Wei

Tao Xiong

Shi Bo Zhang

Lingling Zhang

Jiubin Zhou

In some implementations, a memory device may receive a write command that includes data to be written to multiple memory pages of a translation unit (TU) of the memory device. The multiple memory pages of the TU may span multiple memory planes of the memory device. The memory device may identify the multiple memory pages of the TU, to which the data is to be written, based on one or more bad blocks of the memory device and a determination of whether one or more memory pages of the memory device are to be reserved. The memory device may write the data to the multiple memory pages of the TU.

Read and write address translation using reserved memory pages for multi-page translation units

A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.

Performing memory access operations with a logical-to-physical mapping table with reduced size

A method includes assigning a respective initial credit value to each LUN of a block stripe; performing an erase operation across the block stripe; reducing, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value; refraining from programming to each LUN of the block stripe having a respective reduced credit value equal to zero; and programming to each LUN of the block stripe having a respective reduced credit value greater than zero.

Memory sub-system LUN bypassing

Disclosed herein are methods, apparatuses and systems related to adjusting operation of memory dies according to reliability measures determined in real-time. The apparatus may be configured to determine the reliability measures based on (1) initiating and completing a programming operation within respective timings following an erase operation and (2) reading the programmed data within a window from completing the programming operation.

Apparatus with circuit management mechanism and methods for operating the same

A processing device identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field; identifies a second set of bits associated with the translation unit, wherein the second set of bits corresponds to a block field; updates a first portion of an address mapping table corresponding to the second set of bits with a value representing a difference between a value stored in the page field and a threshold value; updates a second portion of the address mapping table corresponding to the first set of bits with a value representing a block number; determines, based on the updated first portion and the updated second portion, that a swapping condition is satisfied; and performs a data access operation on a set of memory cells residing at a location corresponding to the translation unit.

Smart swapping and effective encoding of a double word in a memory sub-system

Exemplary methods, apparatuses, and systems include erasing a portion of memory from a garbage pool in response to detecting an idle period. A request to write data to the memory is received and it is determined that a charge gain threshold has not been satisfied for the erased portion of memory. The data is written to the erased portion of memory in response to determining the charge gain threshold has not been satisfied.

Write performance optimization for erase on demand

A processing device in a memory system identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field. The processing device identifies a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field. The processing device determines that a value representing a page number stored in the page field satisfies a threshold criterion. Responsive to determining that the value representing the page number satisfies the threshold criterion, the processing device determines a difference between the value representing the page number and a threshold value associated with the threshold criterion plurality of block stripes on a memory device. The processing device stores a value representing the difference as a plurality of bits of the second set of bits. The processing device stores a value representing a block number stored in the block field as a plurality of bits of the first set of bits.

A system includes a line cache, a memory device, and a processing device operatively coupled to the line cache and the memory device, The processing device includes a buffer manager and a high-speed mode driver, the processing device to perform operations including: detecting that a received event is located in an events list, wherein events stored in the events list are associated with a set of functions that are known to cause a clock domain crossing between the buffer manager and a host system; enabling access to the line cache; and running, using the high-speed mode driver, in a high-speed mode to execute the set of functions out of the line cache on behalf of the host system.

Effective avoidance of line cache misses

A first data item is programmed to a first set of logical units of a memory sub-system. The first set of logical units is associated with a first fault tolerant stripe. A second data item is programmed to a second set of logical units of a memory sub-system. The second set of logical units is associated with a second fault tolerant stripe. A first set of redundancy metadata corresponding to the first data item and a second set of redundancy metadata corresponding to the second data item is generated. A combined set of redundancy metadata is generated based on at least the first set of redundancy metadata and the second set of redundancy metadata. The combined set of redundancy metadata is stored at a specified memory device of the memory sub-system.

Redundancy metadata for multi-plane memory access failure

A method is described that includes determining, by a memory subsystem, that a garbage collection process is to be performed on a memory device and selecting a first candidate block stripe for folding into a first target block stripe in response to determining that the garbage collection process is to be performed. The method further includes determining, by the memory subsystem, that a physical-to-logical table stored in the first candidate block stripe is unavailable; reducing a write command rate, which controls a rate at which writes are fulfilled by the memory subsystem, in response to determining that the physical-to-logical table stored in the first candidate block stripe is unavailable; and performing folding of the first candidate block stripe into the first target block stripe using a logical-to-physical table.

Optimizing garbage collection that uses a logical-to-physical table search

Exemplary methods, apparatuses, and systems include reading logical-to-physical (L2P) table entries from non-volatile memory into volatile memory. Upon detection of a trigger to recover L2P data that was unmerged with the L2P table entries, a copy of an L2P journal is read from non-volatile memory. The L2P journal includes the L2P data that was unmerged with the L2P table entries. One or more of the L2P table entries are updated using the L2P data from the L2P journal.

Rebuilding logical-to-physical address mapping with limited memory

A system includes a line cache, a memory device, and a processing device to execute firmware to detect that a received event is located in an events list, wherein events stored in the events list are associated with critical functions that occur no more than once per a threshold number of days and time out after between 15 microseconds and a predetermined number of hundreds of seconds. The firmware is further to enable access to the line cache and execute a critical function associated with the received event out of an always-loaded area of the line cache.

An annular display apparatus and a display device are provided. The annular display apparatus includes a display panel, an integrated circuit chip and a flexible printed circuit. The display panel includes an annular display region, an outer non-display region and an inner non-display region, the display region is provided with multiple control signal lines, the inner non-display region is provided with multiple panel binding interfaces, and the multiple control signal lines are electrically connected to the multiple panel binding interfaces respectively. The flexible printed circuit includes a bonding region and a chip region, the bonding region is provided with multiple circuit board binding interfaces which are bound to to the multiple panel binding interfaces, the chip region is configured to arrange the integrated circuit chip, and the integrated circuit chip is electrically connected to the multiple circuit board binding interfaces.

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Shanghai, China

Meng Wei