Yangtze Memory Technologies Co., Ltd.

Accelink Technologies Co., Ltd.

Meng Wang

Lin Chen

Yunfei Liu

Li Hong Xiao

Jun Chen

Zhenyu Lu

Yushi Hu

Qian Tao

Haihui Huang

Er Jiang Xu

LongDong Liu

Zhen Fang

Peng Chen

Houde Zhou

Liping Sun

Liu Yang

Rui Yang

Zhilin Yuan

Jinping Guo

Yuhong Ma

Lidan Song

Lihong Tang

Dingkang Chen

Xinru Zeng

Baohua Zhang

The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL through the remaining portion of the top surface of the first staircase layer.

Flip-chip stacking structures and methods for forming the same

Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.

Method for forming channel hole plug of three-dimensional memory device

A device area and a marking area neighboring the device area over a dielectric stack are determined. The dielectric stack includes insulating material layers and sacrificial material layers arranged alternatingly over a substrate. The device area and the marking area are patterned using a same etching process to form a marking pattern having a central marking structure in a marking area and a staircase pattern in the device area. The marking pattern and the staircase pattern have a same thickness equal to a thickness of at least one insulating material layer and one sacrificial material layer, and the central marking structure divides the marking area into a first marking sub-area farther from the device area and a second marking sub-area closer to the device area. A first pattern density of the first marking sub-area is greater than or equal to a second pattern density of the second marking sub-area. A photoresist layer is formed to cover the staircase pattern and expose the marking pattern, and the photoresist layer is trimmed to expose a portion of the dielectric stack along a horizontal direction. An etching process is performed to maintain the marking pattern and remove the exposed portion of the dielectric stack and form a staircase.

Marking pattern in forming staircase structure of three-dimensional memory device

Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having insulating layers and conductor layers arranged alternatingly over a substrate along a vertical direction; and a marking pattern having interleaved layers over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area. The central marking structure consists of interleaved layers and divides the marking area into a first marking sub-area and a second marking sub-area. A first pattern density of the first marking sub-area is higher than or equal to a second pattern density of the second marking sub-area.

Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a marking pattern for controlling a trimming rate of a photoresist trimming process includes a plurality of interleaved layers, the plurality of interleaved layers including at least two layers of different materials stacking along a vertical direction over a substrate. In some embodiments, the marking pattern also includes a central marking structure that divides the marking area into a first marking sub-area farther from a device area and a second marking sub-area closer to the device area, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

A method for reducing an epitaxial growth loading effect in a patterned device includes forming a first trench and a second trench in a substrate and in a first insulating layer over the substrate to form a low pattern density region and a high pattern density region. The first trench has a larger cross-sectional area than the second trench. The method further includes isolating the first trench from the second trench by using a first mask. The method further include disposing a second insulating layer in the first trench. The method further includes removing a portion of the first mask in order to expose the second trench. The method further includes growing an epitaxial layer in the second trench.

Methods for solving epitaxial growth loading effect at different pattern density regions

Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. In some embodiments, the semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

The present disclosure describes methods and patterned devices for reducing a loading effect between a low pattern density region and a high pattern density region. The patterned device includes a substrate, a first insulating layer over the substrate, a low pattern density region, a high pattern density region, a second insulating layer, and an epitaxial grown layer. The low pattern density region includes a first trench in the first insulating layer and the substrate. The high pattern density region includes a second trench in the first insulating layer and the substrate. The second insulating layer is formed in the first trench. The epitaxial grown layer is formed in the second trench. The first trench has a larger cross-sectional area than the second trench.

A method for compensating for a wavelength shift in a wavelength selective switch (WSS), and a device therefor. The device comprises a fixed seat () as well as a rotation beam () and a compensation block () that have different thermal expansion amounts, the rotation beam () and the compensation block () being fixedly adhered to the fixed seat (). In the method, a combined structure of the rotation beam () and the compensation block () with different thermal expansion amounts is adopted; the combined structure rotates by means of different expansion amounts generated by the rotation beam () and the compensation block () at the same external temperature, and further drives an optical element of the WSS to rotate, hence compensating for a wavelength shift of the WSS. The method is safe and reliable; the device has a simple structure, and is convenient to encapsulate, is applicable to various WSS optical paths, and does not affect advantages of the optical path structure of the WSS.

Growing community of inventors

Wuhan, China

Meng Wang