Mediatek Corporation

Mediatek Incorporation

Meng-Ta Yang

Pi-Hai Liu

Ping-Ying Wang

Tse-Hsiang Hsu

Hong-Sing Kao

Wen-Yi Wu

Yuh Cheng

Kuan-Hua Chao

Jin-Bin Yang

Tzu-Pai Wang

Hsiang-Ji Hsieh

A delay line calibration mechanism includes a first delay line, a second delay line, a phase detector, and a controller. The first delay line receives a first pulse and a first delay selection signal, and delays the first pulse for a first delay period according to the first delay selection signal to output a first delayed pulse. The second delay line receives a second pulse and a second delay selection signal, and delays the second pulse for a second delay period according to the second delay selection signal to output a second delayed pulse. The phase detector generates a phase difference signal indicating the phase difference between the first delayed pulse and the second delayed pulse by comparing the first delayed pulse and the second delayed pulse. The controller generates the second delay selection signal, and generates the first delay selection signal according to the phase difference signal.

Delay line calibration mechanism and related multi-clock signal generator

An apparatus for maximum likelihood signal detection comprises a reference data unit, a branch metric unit, an add-compare-select unit, a path metric unit and a path memory, and is used for detecting maximum likelihood signal. The reference information unit, the branch metric unit, the add-compare-select unit or the path metric unit can further comprise a multiplexer to removing unnecessary paths according to a control signal. The control signal is adjusted according to channel response, coding constraint or channel memory length.

Apparatus of maximum likelihood signal detection

A delay line calibration mechanism includes a delay line, a phase detector, and a controller. The delay line receives an input pulse, a calibration pulse, a first delay selection signal, and a second delay selection signal, delays the input pulse for a delay period according to the first delay selection signal to output a delayed pulse, and delays the calibration pulse for a calibration delay period according to the second delay selection signal to output a delayed calibration pulse. The controller is for generating the input pulse, the calibration pulse, and a reference pulse. The controller also generates the first delay selection signal, and generates the second delay selection signal according to a phase difference signal. The phase detector is for generating the phase difference signal indicating the difference between the delayed calibration pulse and the reference pulse by comparing the delayed calibration pulse and the reference pulse.

A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal.

Frequency divider, frequency dividing method thereof, and phase locked loop utilizing the frequency divider

An apparatus for controlling discrete data in a disk overwrite area or a power calibration area comprises a signal-processing unit, an address-processing unit, a control signal-processing unit, a clock recovery circuit, a signal-processing unit parameter control unit, and a clock recovery circuit parameter control unit, wherein the control signal-processing unit uses a message produced by a data on the disc to determine the control signals such as hold, load, or increasing bandwidth for holding, loading, and increasing the bandwidth of the parameters for processing the related circuits (such as the circuit of the signal-processing unit or the clock recovery circuit) of the discrete data produced between the two data clusters, so as to increase the convergent speed of the circuits for assuring the accuracy of reading data.

Apparatus for controlling discrete data in disk overwrite area or power calibration area

An ISI cancellation equalizer is disclosed. The ISI cancellation equalizer comprises a non-linear mapping circuit, a filter, a delay circuit, and a combiner. The non-linear mapping circuit generates a mapped signal by mapping a level of an input signal into a predetermined value when the input signal falls in a predetermined region, and linearly maps the level of the input signal when the level of the input signal is beyond the predetermined region. The filter depresses an inter-symbol interference (ISI) in the mapped signal to generate a filtered signal. The delay circuit filters the high boosted signal to generate a delayed signal. The combiner combines the filtered signal and the delayed signal to obtain an equalized signal.

ISI cancellation equalizer

A path metric computing method applied in a high-speed Viterbi detector and related apparatus thereof are disclosed. The path metric computing apparatus includes a comparator for generating a control signal according a plurality of previous path metrics, a combining circuit for generating a plurality of first output values according to the previous path metrics and branch costs of a plurality of branches of a current state, and a multiplexer, electrically connected to the comparator and the combining circuit, for determining a first path metric of the current state according to the control signal and the output values.

Method of computing path metrics in a high-speed Viterbi detector and related apparatus thereof

A loop latency compensated phase-locked loop (PLL). The loop latency compensated PLL comprises an ADC, a phase detector, a loop filter and a VCO. The ADC receives an analog input signal and an output clock to generate a digital signal. The phase detector receives the digital signal to generate an estimated phase error. The loop filter receives the estimated phase error to generate a latency compensated phase error output signal with a phase assigned by a sign-bit of the received estimated phase error. The VCO generates the output clock in response to the latency compensated phase error output signal and feeds the output clock back to the ADC.

Loop latency compensated phase-locked loop

A phase detection device comprising an analog-digital converter, an interpolator, and a determining unit. The analog-digital converter receives an analog signal and converts the analog signal to a digital signal according to a plurality of digital sampling points. The interpolator generates a plurality of interpolation points according to a predetermined amount of digital sampling points. The determining unit obtains a phase of the ZC point according to the interpolation points or the digital sampling points.

Phase detection device and method thereof

An adaptive equalizer and the related method are disclosed. The adaptive equalizer is capable of adjusting its own equalization coefficients, and includes a reference signal generator for generating a reference signal according to a first reference source, an equalization unit for generating an equalized signal by processing a received signal through a plurality of equalization coefficients, a weighted signal generator for generating a weighted signal according to a second reference source, and a coefficient adapting circuit for adjusting the equalization coefficients according to the reference signal, the equalized signal, the weighted signal, and the received signal.

Adaptive equalizer and related method thereof

The invention discloses a decoding apparatus and the method thereof for decoding a signal retrieved by an optical information reproducing system from an optical information recording medium. N legal codes are predetermined. According to the invention, first, the retrieved signal is converted into a data stream. Then, in a Viterbi decoding manner, the data stream is decoded into a digital code in accordance with a level of the data stream and N reference levels. Then, the binary code is decoded by a binary array into one of the N legal codes, and each of the N legal codes corresponds to one of N reference levels. In particular, the N reference levels are corrected by various detected conditions to enhance the correctness of decoded data.

Decoding apparatus and method of optical information reproducing system

A digital PLL system includes a first multiplier coupled to a phase difference signal for multiplying the phase difference signal by a first gain factor; a second multiplier coupled to the phase difference signal for multiplying the phase difference signal by a second gain factor; a digital loop filter coupled to the first multiplier and the second multiplier for providing an integral signal and a proportional signal and for generating a control signal according to the integral signal and the proportional signal; and an auto-gain control (AGC) unit coupled to the first multiplier, the second multiplier, and the digital loop filter. The AGC unit further comprises a first control unit for updating the first gain factor according to the integral signal; and a second control unit for updating the second gain factor according to the proportional signal.

Auto-gain controlled digital phase-locked loop and method thereof

A read channel apparatus is disclosed for reading data recorded on an optical storage system. An exemplary sampling device samples an analog read signal generating from the optical storage system to generate a sequence of sample values. A subtractor subtracts an estimated DC offset from the sample values to generate a sequence of DC-removed sample values. An equalizer equalizes DC-removed sample values in accordance with a target spectrum to generate a sequence of equalized sample values. First and second interpolators interpolate the equalized sample values to respectively generate sequences of even-time sample values and odd-time sample values. A data sequence composed of the even-time and the odd-time sample values is substantially synchronized to the baud rate. A timing recovery controller controls the interpolators to synchronize the even-time and odd-time sample values to the baud rate.

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Miao-Li Hsien, Taiwan

Meng-Ta Yang