United Microelectronics Corp.

Meng-Ping Chuang

Yu-Tse Kuo

Chun-Hsien Huang

Chien-Hung Zordius Chen

Shu-Ru Wang

Chun-Yen Tseng

Li-Ping Huang

Ching-Cheng Lung

Hsin-Chih Yu

Yun-San Huang

Chia-Chun Sun

Tong-Yu Chen

Hsueh-Hao Shih

Yu-Fang Chen

A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Layout of semiconductor memory device

The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.

Semiconductor layout pattern and forming method thereof

A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL), a first pull-down transistor (PD), a second (PL), and a second pull-down transistor (PD) on the substrate, and a first pass gate transistor (PGA), a second pass gate transistor (PGB), a third pass gate transistor (PGA) and a fourth pass gate transistor (PGB), wherein the PGA and the PGB comprise a first fin structure, the PGA and the PGB comprise a second fin structure, a first local interconnection layer disposed between the PGA and the PGB and disposed on the fin structures of the PLand the PD, a second local interconnection layer disposed between the PGA and the PGB and disposed between the fin structures of the PLand the PD, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

Static random access memory structure

A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL), a first pull-down transistor (PD), a second (PL), and a second pull-down transistor (PD) on the substrate, and a first pass gate transistor (PGA), a second pass gate transistor (PGB), a third pass gate transistor (PGA) and a fourth pass gate transistor (PGB), wherein the PGA and the PGB comprise an identical first fin structure, the PGA and the PGB comprise an identical second fin structure, a first local interconnection layer disposed between the PGA and the PGB and disposed on the fin structures of the PLand the PD, a second local interconnection layer disposed between the PGA and the PGB and disposed between the fin structures of the PLand the PD

Layout pattern for static random access memory

A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

Semiconductor memory device

A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions, a plurality of second regions, a plurality of third regions, and a plurality of fourth regions, and each first region includes the memory cell. Each second region, each third region and each fourth region include a voltage contact to provide a voltage to the first P-type well region, the second P-type well region, and the N-type well region. The first region to the fourth region do not overlap with each other.

A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.

Growing community of inventors

Hsinchu, Taiwan

Meng-Ping Chuang