Taiwan Semiconductor Manufacturing Comp. Ltd.

Meng-Pei Lu

Ming-Han Lee

Shin-Yi Yang

Shau-Lin Shue

Yu-Chen Chan

Chin-Lung Chung

Shu-Wei Li

Hsin-Yen Huang

Chao-Hsien Peng

Ching-Fu Yeh

Shih-Kang Fu

Tz-Jun Kuo

Guanyu Luo

Cian-Yu Chen

Yun-Chi Chiang

Andy Li

A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes an interconnect structure which includes a topological material. The topological material includes a topological insulator, a topological semimetal, or a combination thereof. A method for manufacturing the semiconductor device is also disclosed.

Interconnect structure including topological material

The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.

Integrated chip with graphene based interconnect

A method for forming a semiconductor structure includes following operations. A hybrid layered structure is formed. The hybrid layered structure includes at least a 2D material layer and a first 3D material layer. Portions of the hybrid layered structure are removed to form a plurality of conductive features and at least an opening between the conductive features. A dielectric material is formed to fill the opening and to form an air gap sealed within.

Method for forming semiconductor structure

A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure comprises at least one two-dimensional (2D) conductive structure; a dielectric layer disposed on the 2D conductive structure; and at least one interconnect structure disposed in the dielectric layer and extending into the 2D conductive structure, wherein the interconnect structure laterally connects to at least one edge of the 2D conductive structure.

Semiconductor structure with two-dimensional conductive structures

A semiconductor device includes an interconnect structure embedded in a first metallization layer comprising a dielectric material. The interconnect structure includes a first metal material. The semiconductor device includes a first liner structure embedded in the first metallization layer. The first liner structure is extended along one or more boundaries of the interconnect structure in the first metallization layer. The first liner structure includes a second metal material reacted with one or more dopants, the second metal material being different from the first metal material.

Semiconductor device including liner structure

In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.

Protection liner on interconnect wire to enlarge processing window for overlying interconnect via

A semiconductor structure includes a substrate, a plurality of conductive features disposed over the substrate, and an isolation structure between conductive features and separating the conductive features from each other. Each of the conductive features includes a first metal layer and a 2D material layer. Another semiconductor structure includes a first conductive feature, a dielectric structure over the first conductive feature, a second conductive feature in the dielectric structure and coupled to the first conductive feature, and a conductive line over and coupled to the second conductive feature. In some embodiments, the conductive line includes a first 3D material layer, a first 2D material layer, and a second 3D material layer. The first 2D material layer is disposed between the first 3D material layer and the second 3D material layer.

Semiconductor structure and method for forming the same

Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.

Via structure and methods for forming the same

A method includes forming a first metal into a first trench in a dielectric layer, performing a thermal treatment to the first metal such that an average grain size of the first metal is increased, and performing a first chemical mechanical polish (CMP) process to the first metal after the performing the thermal treatment.

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Hsinchu, Taiwan

Meng-Pei Lu