Globalfoundries U.S. Inc.

Meng Miao

Robert J Gauthier, Jr

Souvick Mitra

Alain F Loiseau

You Li

Wei Liang

Tsung-Che Tsai

Anindya Nath

Alain François Loiseau

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.

Fin-based and bipolar electrostatic discharge devices

Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.

Integrated circuit structure with avalanche junction to doped semiconductor over semiconductor well

A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

Operating voltage-triggered semiconductor controlled rectifier

Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P− closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.

Semiconductor-controlled rectifier with low trigger voltage for electrostatic discharge protection

An ESD protection device may be provided, including: a substrate including a first conductivity region and a second conductivity region arranged therein. The first conductivity region may include a first terminal region and a second terminal region electrically coupled with each other. The second conductivity region may include a third terminal region and a fourth terminal region electrically coupled with each other. The second conductivity region may further include a fifth terminal region electrically coupled with the first and second terminal regions. The fifth terminal region may be arranged laterally between the third terminal region and the fourth terminal region. The first conductivity region, the first terminal region, the third terminal region, and the fifth terminal region may have a first conductivity type. The second conductivity region, the second terminal region, and the fourth terminal region may have a second conductivity type different from the first conductivity type.

Electrostatic discharge protection devices and methods for fabricating electrostatic discharge protection devices

Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.

Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.

Structure and method for controlling electrostatic discharge (ESD) event in resistor-capacitor circuit

The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge (ESD) device and methods of manufacture. The structure (ESD device) includes: a trigger collector region having fin structures of a first dopant type, a collector region having fin structures in a well of a second dopant type and further including a lateral ballasting resistance; an emitter region having a well of the second dopant type and fin structures of the first dopant type; and a base region having a well and fin structures of the second dopant type.

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Williston, VT, United States of America

Meng Miao