Imec Vzw

Katholieke Universiteit Leuven

Meng Li

Yanxiang Huang

Chunshu Li

The present disclosure relates to an error resilient scheme for a signal processing device configured to perform iterative processing on clocked input data and to provide output data. The signal processing device includes a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to provide or generate processed data, and a selection circuit configured to provide as the output signal either the processed data or the clocked input data, depending on a control signal representative of a set-up timing error detected in an input data.

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Leuven, Belgium

Meng Li