Taiwan Semiconductor Manufacturing Comp. Ltd.

Meng-kai Hsu

Hui-Zhong Zhuang

Anurag Verma

Jerry Chang Jui Kao

Chih-wei Chang

Cheng-yu Lin

Pochun Wang

Wei-Ling Chang

Sheng-hsiung Chen

Johnny Chiahao Li

Sang-Chi Huang

Shang-chih Hsieh

Shi-han Zhang

You-cheng Lai

Chi-Chun Liang

Pei-Wei Liao

A semiconductor device, method, and system of arranging patterns of the same are provided. The method includes generating a plurality of gate patterns and conductive patterns, wherein each of the plurality of gate patterns and conductive patterns is located at a first horizontal level and extends along a first direction. The method also includes selecting one of the gate patterns as an input pin or one of the conductive patterns as an output pin. The method further includes generating, based on a selected gate pattern or a selected conductive pattern, a plurality of metallization patterns. Each of the plurality of metallization patterns is located at a second horizontal level overlying the first horizontal level and extends along a second direction substantially perpendicular to the first direction.

Semiconductor device and method and system of arranging patterns of the same

A method including: providing a design data of an integrated circuit (IC), the design data comprising a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is electrically connected between an input terminal of the first cell and an output terminal of the first cell; providing a library of the first cell, wherein the library includes a table of timing or power parameters of the first cell based on a multidimensional input set associated with the critical internal net; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data.

Standard cell characterization for internal conductive line of cell

A layout method and a semiconductor device are disclosed. The layout method includes: generating a design layout by placing a cell, wherein the cell includes: a first conductive segment overlapping a source/drain region and disposed immediately adjacent to a first power rail, wherein the first conductive segment has a length substantially equal to a cell length; a second conductive segment; and a third conductive segment between the first and second conductive segments. The layout method further includes: providing a fourth conductive segment and a fifth conductive segment to the design layout, wherein the fourth and fifth conductive segments are aligned in a first direction.

Routing structure of semiconductor device and forming method thereof

The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.

Method for generating routing structure of semiconductor device

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HSINCHU COUNTY, Taiwan

Meng-kai Hsu