Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Springsoft, Inc.

Springsoft Usa, Inc.

Meng-Kai Hsu

Wen-Hao Chen

Yuan-Te Hou

Yao-Wen Chang

Hui-Zhong Zhuang

Lee-Chung Lu

Po-Hsiang Huang

Yi-Kan Cheng

Sheng-Hsiung Chen

Fong-yuan Chang

Chin-Chou Liu

Chi-Yu Lu

Pin-Dai Sue

Wai-Kei Mak

Yu-Hsiang Cheng

Jung-Chou Tsai

Ting-Chi Wang

Ding-Wei Huang

Prasenjit Ray

Chih-Wei Chang

Anurag Verma

Shih-Chun Chen

Chao-Hung Wang

Yen-Yi Wu

Chung-Hsing Wang

Chin-Chang Hsu

Ke-Ying Su

Hsien-Hsin Sean Lee

Chi-Yeh Yu

Chin-Hsiung Hsu

King-Ho Tam

Tung-Chieh Chen

Chia-Ming Ho

Kuang-Hung Chang

Adari Rama Bhadra Rao

Valeriy Balabanov

A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Method and system for generating layout diagram including wiring arrangement

A method includes clustering cells in a group of cells into a selected number of clusters, and ranking the clusters based on a list of prioritized features to generate a list of ranked clusters. The method also includes ranking cells in each of one or more ranked clusters in the list of ranked clusters, based on the list of prioritized features, to generate a list of ranked critical cells. The method further includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.

Method of analyzing and detecting critical cells

A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

System for generating layout diagram including wiring arrangement

A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Method for generating layout diagram including wiring arrangement

A method (of generating a layout diagram) includes identifying, in the layout diagram, a group of three or more cells arranged so as to exhibit two or more edge-pairs (EPs) that are edge-wise abutted relative to a first direction. The method further includes, for each of at least one but fewer than all of the three or more cells, selectively moving a given one of cells corresponding to one of the members of the corresponding EP resulting in at least a minimum gap in the first direction between the members of the corresponding EP.

Method and system of generating a layout diagram

A method includes obtaining a feature vector for each cell in a group of cells. The feature vector for a cell includes a score value for each feature in a set of features selected for characterizing the group of cells. The method includes clustering cells in the group into a selected number of clusters, based on distances between end points of feature vectors of the cells. The method includes generating a list of ranked critical cells in the selected number of clusters based on a list of prioritized features associated with the set of features. The method includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.

A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.

Method of decomposing a layout for multiple-patterning lithography

A semiconductor apparatus includes a first cell having a first interconnect structure and a second cell having a second interconnect structure. The semiconductor apparatus further includes a first plurality of conductive segments, wherein each conductive segment of the first plurality of conductive segments directly connects a first metal level of the first interconnect structure to a first metal level of the second interconnect structure. The semiconductor apparatus further includes a third cell having a third interconnect structure and a fourth cell having a fourth interconnect structure. The semiconductor apparatus further includes a second plurality of conductive segments, wherein each conductive segment of the second plurality of conductive segments directly connects a second metal level of the third interconnect structure to a second metal level of the fourth interconnect structure, and the second metal level is different from the first metal level.

Semiconductor apparatus including uncrowned and crowned cells and method of making

Method and system of revising a layout diagram

A method related to legalize mixed-cell height standard cells of an IC is provided. A global placement of the IC is obtained. A plurality of standard cells of the IC are placed in the global placement. Each standard cell is moved from a position to the nearest row in the global placement. A displacement value of each moved standard cell is obtained in the global placement. The global placement of the IC is divided into a plurality of windows according to the displacement values of the moved standard cells in each window and a dead space corresponding to each moved standard cell in each window. All overlapping areas among the standard cells of each window are removed to obtain a detailed placement. The IC is manufactured according to the detailed placement. The standard cells have different cell heights in each window.

Method for legalizing mixed-cell height standard cells of IC

A method is disclosed that includes: if there is a conflict graph including a sub-graph representing that each spacing between any two of three adjacent patterns of quadruple-patterning (QP) patterns in at least one of two abutting cells is smaller than a threshold spacing, performing operations including: identifying if one of edges that connect the three adjacent patterns of QP patterns to one another is constructed along, and/or in parallel with, a boundary between the two abutting cells; modifying multiple-patterning patterns of a layout of an integrated circuit (IC) to exclude patterns representing the sub-graph; and initiating generation of the IC from the modified multiple-patterning patterns, wherein at least one operation of identifying, modifying, or initiating is performed by at least one processor.

Rule checking for multiple patterning technology

A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)&#x2dc;M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array, the latter including a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)&#x2dc;M(N+Q) metallization layers. The crowning includes disposing vias in a VIA(N+1) layer so as to be substantially collinear (relative to a first direction), and not substantially collinear (relative to a substantially perpendicular second direction), with corresponding vias in the VIA(N) layer.

Method of reconfiguring uncrowned standard cells and semiconductor apparatus including uncrowned and crowned cells

A method for legalizing mixed-cell height standard cells of an IC is provided. A target standard cell is obtained in a window of a global placement. The target standard cell has a first area overlapping a first standard cell located in a first row of the window, and a second area overlapping a second standard cell located in a second row of the window. The target standard cell and the first standard cell are moved until the target standard cell does not overlap the first standard cell in the first row of the window. The target standard cell and the first standard cell are clustered as a first cluster when the target standard cell does not overlap the first standard cell. The first cluster is moved away from the second standard cell in the second row until the second standard cell does not overlap the first cluster.

Growing community of inventors

Xinfeng, China

Meng-Kai Hsu