United Microelectronics Corp.

Meng-Jin Tsai

Kun-Lin Wu

Cheng-Han Huang

Water Lur

Jih-Wen Chou

Shih-Wei Sun

Wen-Kuan Yeh

Coming Chen

Yimin Huang

Heng-Sheng Huang

Po-Hung Chen

Kun-Cho Chen

Chen-Wei Lee

Ching-Chun Hwang

Wei-Chung Chen

Ta-Chi Kuo

Chin-Lai Chen

Cheng-Jung Hsu

Kuang-Chung Cheng

Kuo-Jaan Su

Te-Chuan Liao

Fei-Hung Chen

A chemical-mechanical polishing process includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiHCl) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

Chemical mechanical polishing method

A chemical-mechanical polishing process for forming a conductive interconnect includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2Cl.sub.2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

Chemical-mechanical polishing method

A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Angstroms can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiHCl) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 &#x212b; can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiHCl) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

A method is provided for forming separated spacer structures in a mixed-mode integrated circuit, which can be used to form spacer structures with different widths for the various kinds of devices in the mixed-mode integrated circuit. The method is for use on a semiconductor substrate which is formed with at least a first gate for a first kind of device of the mixed-mode integrated circuit and a second gate for a second kind of device of the integrated circuit, with the second gate being larger in width than the first gate such that the first gate is formed with a first spacer structure on the sidewalls thereof to a first desired width while the second gate is formed with a second spacer structure on the sidewalls thereof to a second desired width larger than the first desired width. The method features a two-step etching process in which the first etching process is performed to form one spacer structure to the first desired width, while the second etching process is performed to form the other spacer structure to the second desired width.

Method of forming separated spacer structures in mixed-mode integrated circuits

A monitor method for testing probe pins is described in this invention. In accordance with the method of the present invention, a particular probe pin with short, deformity or unstable contact is identified.

Monitor method for testing probe pins

A method for forming enhanced field oxide (FOX) region of low voltage devices in a high voltage process is disclosed. The method includes providing a semiconductor structure comprising a substrate, two field oxide regions on the substrate, a well between the two field oxide regions in the substrate and a silicon nitride layer between the two field oxide regions above the well. As a key step, nitrogen is implanted into the semiconductor structure, and the silicon nitride layer is then removed. Then, a gate oxide layer on the well and silicon oxynitride layer on the field oxide regions are all formed in-situ.

Method for forming enhanced FOX region of low voltage device in high voltage process

A method of manufacturing shallow trench isolation structure comprising the steps of forming a polysilicon mask layer over a substrate, and then patterning the polysilicon mask layer and the substrate to form a trench. Thereafter, a silicon nitride layer is formed covering the sidewalls of the trench. Next, a high-density chemical vapor deposition method is used to deposit oxide material into the trench. Finally, the surface is polished to remove a portion of the oxide layer and the silicon nitride layer until the polysilicon mask layer is exposed. The shallow trench isolation structure can avoid subthreshold kink effect and reduce subthreshold leakage current.

Method of manufacturing shallow trench isolation structure

A metal-insulator-metal capacitor for improved mixed-mode capacitor in a logic circuit of a semiconductor device is disclosed. The bottom electrode of the capacitor is polycide and the top electrode is metal formed by damascene technology. The middle layer of the capacitor is a dielectric layer formed by using a chemical vapor deposition method. The voltage coefficient of this capacitor is approximate to zero.

Metal-insulator-metal capacitor

A method for providing triangle shapes of high-density plasma CVD film, thereby the grad and source/drain implantation can be applied in the same step, and an offset source/drain mask layer can be eliminated. A substrate is provided incorporating a device, wherein the device is defined as a high-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxides is spaced from another of the field oxides by a high-voltage MOS region. Then, a gate oxide layer is formed above the silicon substrate. Moreover, a polysilicon layer is deposited over the gate oxide layer. A photoresist layer is formed above the polysilicon layer and gate oxide layer, wherein the photoresist layer is defined and etched to form a gate. Then, the photoresist layer is removed. Consequentially, a dielectric layer is deposited and etched above the polysilicon layer by using high-density plasma CVD to result in the inherit triangle shape of high-density plasma CVD film characteristic. N-type ions are implanted into the silicon substrate to form N-type grad therein, and then N,-type ions only penetrate through the flat high-density plasma CVD dielectric film and not the triangle shape high-density plasma CVD film to form source/drain regions inside the N-type grad.

Method for fabricating high-voltage device

A method for improving the damascene process window for metallization utilizes an anti-reflective coating to increase the precision of the photolithography process. An inter-layer dielectric and an anti-reflective layer are formed in turn on a semiconductor substrate. The inter-layer dielectric is patterned to form the interconnecting line regions. A conductive layer is then deposited on the semiconductor substrate and fills the interconnecting line regions. The chemical mechanical polish is performed to remove a portion of the conductive layer exceeding the interconnect line regions and simultaneously remove residual portion of said anti-reflective layer.

Damascene process with anti-reflection coating

A method for fabricating a photodiode is described in which a pad oxide layer and a silicon nitride layer are sequentially formed on a provided substrate. The silicon nitride layer, and the pad oxide layer and the substrate are sequentially patterned to form an opening in the substrate. A spacer is formed on the sidewall of the opening. With the spacer and the silicon nitride layer serving as a mask, the substrate is etched forming a trench in the substrate. An oxide plug is then formed filling the trench and the opening using the conventional shallow trench fabrication method. A P-well region and an N-well region are formed respectively on two sides of the trench. An N+ type region and a P+ type region are formed respectively on two sides of the opening; wherein the N+ type region is located above the P-well region and the P+ type region is located above the N-well region

Fabrication method of isolation structure photodiode

A method of fabricating a shallow trench isolation includes formation of a trench in a substrate. An oxide layer is formed on the substrate to fill the trench. A barrier layer and a coating layer are formed in sequence over the substrate. A first etching step is performed to remove a portion of the coating layer and the oxide layer to at least expose the oxide layer on the mask layer. A second etching step is performed to remove the other portion of the coating layer and the oxide layer until exposing the mask layer. Thus, micro-scratches and defects do not happen and thus the invention prevents the occurrence of bridging effect and short circuits.

Method of fabricating a shallow trench isolation

A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 .ANG. can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2 Cl.sub.2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

A method for manufacturing mixed-mode devices that can eliminate watermarks resulting from the formation of residues at the dead corner space of an inverted trapezium-shaped structure at the upper end of a shallow trench during dual gate-oxide processing operation. This method uses the same chemical processing conditions for etching the oxide layer and the removal of photoresist layer, so that no watermarks remain after the etching and cleaning processes. MOS transistors are formed over the thin gate oxide layer region and the thick gate oxide region are of, two types, each having a different gate oxide layer thickness so that each has a different operating voltage.

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Kaohsiung, Taiwan

Meng-Jin Tsai