Faraday Technology Corporation

Other

Meng-Jer Wey

Chih-Hung Wu

Jeng-Huang Wu

Chien-Hui Chuang

Chu Yu Chin

Yi-Ren Hwang

A pre-buffer level shifter and an I/O buffer apparatus are provided. The pre-buffer level shifter includes a switchable current source, a current mirror, a buffer unit, a first clamping circuit and a second clamping circuit. Because of a clamping circuit inside a thin oxide MOS transistor device of the pre-buffer level shifter, the present invention can control the voltage swing of the signal for driving an output buffer within a suitable voltage range. Thus, the pre-buffer level shifter can correctly drive the output buffer made of thin oxide MOS transistor devices, increase the operating speed and ensure the reliability thereof.

Pre-buffer level shifter and input/output buffer apparatus

A programmable level shifter. The programmable level shifter comprises a first P-type FET, a first N-type FET, a second P-type FET, a second N-type FET, and a programmable device. The first P-type FET is coupled between a fist power line and a non-inverted output node, and a gate pole thereof is coupled to a inverted output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the non-inverted output node, which can be programmed to change an effective resistance between the first power line and the inverted output node when the second P-type FET is turned on.

Programmable level shifter for wide range operation purpose

A programmable level shifter. The programmable level shifter comprises a first P-type FET, a second P-type FET, a third P-type FET, a fourth P-type FET, a fifth P-type FET, a sixth P-type FET, a first N-type FET, a second N-type FET, a third N-type FET, and a programmable device. The first P-type FET is coupled between a first power line and an output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the output node, which can be programmed to change an effective resistance between the first power line and the output node when the second P-type FET is turned on.

Level shifter for wide range operation

A programmable level shifter. The programmable level shifter comprises a first P-type FET, a first N-type FET, a second P-type FET, a second N-type FET, an inverter, and a programmable device. The first P-type FET is coupled between a fist power line and an output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the output node, which can be programmed to change an effective resistance between the first power line and the output node when the second P-type FET is turned on.

A high-speed output transconductance amplifier (OTA) capable of operating at different voltage levels. The high-speed output transconductance amplifier configures a cross-coupled circuit with programmable switches to offer a high-speed receiver capable of operating at lower voltage and normal voltage, for example, a receiver can be operated in both for SSTL-3 (3.3V system) and SSTL-2 (2.5V system).

High-speed output transconductance amplifier capable of operating at different voltage levels

A programmable multi-configuration output buffer circuit having an input port terminal and an output port terminal. The output buffer circuit includes an output buffer stage having no delay unit and one or more output buffer stages having a delay unit. The output buffer stage having no delay unit includes a first type channel pull up transistor, a second type channel pull down transistor and a first logic circuit. The drain terminal of the first type channel pull up transistor and the second type channel pull down transistor are connected together and connected with the output port as well. The first logic circuit receives an enable signal and an input signal. The output buffer stage having a delay unit therein includes a first type channel pull up transistor, a second type channel pull down transistor and a second logic circuit. The drain terminal of the first type channel pull up transistor and the second type channel pull down transistor are connected together and connects with the output port as well. The second logic circuit is connected to the enable signal, the input signal and a corresponding select enable signal. The output buffer circuit may further includes a programmable storage unit for controlling output configuration. When the output buffer circuit is programmed, select enable signals can be outputted so that a portion of the output buffer stages having a delay unit can be triggered.

High-speed, low-noise, impedance-matched output buffer circuit

The high-speed, low setup time, voltage-sensing flip-flop of an embodiment of the present invention comprises a master stage and a slave stage. The master stage has a data input and a clock input. The slave stage receives two signal lines from the master stage. When the clock input is low, the two input lines to the slave stage are pulled high. This turns on two transistors and precharges the inputs to the slave stage. When the clock makes a high transition, the pullup transistors in the master stage are turned off which decouples the inputs of the slave stage from the output of the master stage. At this time, if the data input is high, the A input to the slave stage is discharged. If the data input is low, the B input to the slave stage is discharged. After the two inputs to the slave stage are decoupled from the master stage, any change in the data input signal causes the inputs to the slave stage to float low since the two lines are not pulled high or low. In this way, the inputs to the slave stage are precharged and discharged on every clock cycle. This precharging results in a nearly zero setup time.

Growing community of inventors

Hsinchu, Taiwan

Meng-Jer Wey