Vanguard International Semiconductor Corporation

Industrial Technology Research Institute

Meng-Jaw Cherng

Ing-Ruey Liaw

Liang-Gi Yao

Sen-Huan Huang

Yeur-Luen Tu

Daniel Hao-Tien Lee

Kwong-Jr Tsai

William W Lee

Pei-Wen Li

Jau-Hwang Ho

John C Lin

A method for making interlevel contacts having low contact resistance (R ) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi ) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide inter connecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon-layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings. The second polysilicon-to-first polysilicon interface formed in the contacts results in consistently low contact resistance (R ). This low R is difficult to achieve in the prior art where the second level metallurgy contacts the first tungsten silicide of the first level interconnecting polycide layer.

Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits

A method for making interlevel contacts having low contact resistance (R.sub.c) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi.sub.2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide interconnecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings. The second polysilicon-to-first polysilicon interface formed in the contacts results in consistently low contact resistance (R.sub.c). This low R.sub.c is difficult to achieve in the prior art where the second level metallurgy contacts the first tungsten silicide of the first level interconnecting polycide layer.

Method for making polycide-to-polycide low contact resistance contacts

A metal layer (24) is formed on an isolation layer (22) to act as interconnections. Subsequently, a thin liner layer (26) is optionally formed along the surface of the metal layer (24) to serve as a buffer layer. An undoped silicate glass (USG) layer (28) is deposited on the liner layer (26). The USG layer (28) is formed using ozone and tetraethylorthosilicate (TEOS) as a source at a temperature of approximately 380 to 420.degree. C. Oxygen gas is used as a carrier for the ozone. The flow rate of the oxygen gas is approximately 4000 to 6000 sccm. Helium gas is used as a carrier for the TEOS. The flow rate of the helium is approximately 3000 to 5000 sccm. A silicon nitride layer (30) is deposited on the USG layer (28) using plasma enhanced chemical vapor deposition (PECVD). The silicon nitride layer (30) serves as a main passivation layer. The thickness of the silicon nitride layer (30) is approximately 3000 to 7000 angstroms.

Method of fabricating a passivation layer for integrated circuits

A method for fabricating very narrow contacts on semiconductor substrate for increasing the packing density of devices on Ultra Large Scale Integration (ULSI) circuits was achieved. The method involves using conventional photolithographic techniques and anisotropic plasma etching to etch openings in a conducting layer and partially etch into an underlying planar insulating layer that covers and isolates the devices and device contact areas. Another conformal conducting layer is deposited on the substrate and in the openings and then etched back to form sidewall spacers in the openings. Using the original conducting layer and the sidewall spacers as an etch mask, the planar insulating layer is anisotropically etched within the sidewall spacers to form very narrow (small) contact opening to the desired device contact areas. Still another conducting layer is then deposited to fill the very narrow contact openings making electrical contact to the device contact areas, and then the conducting layers are patterned to form the next level of connecting metallurgy.

Small contacts for ultra large scale integration semiconductor devices

A method for fabricating small contact openings in the polysilicon/metal 1 dielectric (PMD) layer on semiconductor substrates using polymer sidewall spacers was achieved. This extends the current photoresist resolution limits while simplifying the manufacturing process. The method involves depositing a polysilicon layer on the PMD layer and using a photoresist mask having openings over device contact areas in the substrate. The polysilicon layer is then patterned to form openings with vertical sidewalls to the PMD insulating layer. The contact openings are then anisotropically plasma etched in a gas mixture that simultaneously forms polymer sidewall spacers on the sidewalls in the openings in the polysilicon layer. These sidewall spacers further reduce the contact opening size. The remaining photoresist layer and polymer sidewall spacers are simultaneously removed to complete the narrow contact openings. This method eliminates the need to use an additional deposition and etch-back step to form the sidewalls. A metal layer is then deposited and patterned to form the metal contacts and first level of interconnections.

Method for etching polymer-assisted reduced small contacts for ultra

A method of fabricating double and multi-cylindrical storage capacitors is provided. To form a double crown capacitor, a conductive layer is formed on a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole provided in the underlying insulation structure to thereby electrically connect the conductive layer with an active region of a transistor. A groove is formed in the conductive layer defining an area for a plurality of separated electrodes. First spacers are formed on the side walls of the groove. Then, the conductive layer is anisotrophically etched using the spacers as an etch mask thus forming an annular ridge around the area where the memory device is formed. The first spacers are then removed. Second and third spacers are then formed on the both sidewalls of the annular ridge. Again, the conductive layer is anisotrophically etched using the second and third spacers as an etch mask thus forming a double crown electrode from the remaining conductive layers under the second/third spacers. A capacitor dielectric layer and a top plate electrode layer are formed over the crown electrodes to complete the capacitor. The process of forming spacers on the sidewalls of the groove and on the annular ridge can be repeated to form multi-cylindrical (three or more walls) capacitors.

Method for fabricating a multiple walled crown capacitor of a

A method for manufacturing an array of dynamic random access memory (DRAM) cells having a single crown-shaped or a double crown-shaped stacked capacitors is accomplished. The method involves forming an array of device areas on a silicon substrate in which FETs for the DRAM cells are formed. After forming bit line contacts and bit line metallurgy contacting one of the two source/drain areas of each FET, a thick low melting temperature glass (BPSG) is deposited and planarized by annealing. Node capacitor contact openings are formed in the BPSG using a polysilicon sidewall method that reduces the contact size, and a thick polysilicon layer is deposited to contact the node source/drain areas of the FETs, and also provides a planar polysilicon surface. A specially designed edge phase-shift mask is then used with a positive photoresist to pattern the thick polysilicon layer and form crown-shaped bottom electrodes. The capacitors are then completed by depositing a interelectrode dielectric and forming a polysilicon top electrode. A second phase-shift mask design is used to form a double crown-shaped capacitor. These new capacitors are estimated to increase the capacitance over the more conventional thick capacitor by about 50 and 115%, respectively.

Method for manufacturing crown-shaped storage capacitors on dynamic

A method is provided for fabricating a single crown electrode for a capacitor for semiconductor memory devices. A conductive layer is formed over a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole to thereby electrically connect the conductive layer with an active region of a transistor formed in the substrate Next, a novel groove is etched in the conductive layer between adjacent memory cells. Sidewall spacers are formed on the groove. The conductive layer is anisotropically etched using the spacers as an etching mask, thereby forming a plurality of electrodes having upright portions. The etching exposes the first insulation layer in the area under the grooves, but leaves a thickness of the base conductive layer to form the bottom of the electrode. The spacers then are removed and a conformal dielectric layer is formed over the surface. Lastly, a top plate electrode is formed over the conformal dielectric layer.

Method for fabricating crown capacitors for a dram cell

An improved method for fabricating dynamic random access memory (DRAM) cell having a fin-shaped capacitor with increased capacitance was achieved. The capacitor is fabricated over the bit lines and makes contact to the source/drain area of a field effect transistor (FET). The capacitor with increased capacitance is formed by depositing an N doped polysilicon layer making electrical contact to the source/drain of the FET. A sacrificial oxide layer is deposited and a contact opening formed over the DRAM cell area to the polysilicon layer. A second polysilicon layer is deposited and patterned over the sacrificial oxide layer forming the top fin portion of the capacitor, which makes electrical contact to the first polysilicon layer through the contact opening. The sacrificial oxide layer is then completely removed by wet etching, while the underlying polysilicon layer provides a very important etch stop to protect the substrate structures. The top fin shaped portion of the capacitor is then used very effectively as a mask to anisotropically etch the bottom polysilicon layer, thereby forming a lower fin structure that is aligned to the top fin structure of the capacitor.

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Hsinchu, Taiwan

Meng-Jaw Cherng