Nan Ya Technology Corporation

Nanaya Technology Corporation

Meng-Hung Chen

Shian-Jyh Lin

Chung-Yuan Lee

Chia-Sheng Yu

Pei-Ing Paul Lee

Neng-Tai Shih

Hung-Chang Liao

Yu-Sheng Shu

Ming Hung Lo

A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.

Memory device with a length-controllable channel

A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.

Memory device and fabrication method thereof

A method for forming a deep trench structure comprises the steps of providing a silicon substrate; forming a mask layer of a predetermined pattern on the silicon substrate to expose a portion of the silicon substrate; forming a first trench in the exposed portion of the silicon substrate, the first trench having a first depth; forming a nitride layer on the surfaces of the whole structure; forming a second trench in the first trench downward, the second trench having a second depth greater than the first depth; forming another nitride layer on the surfaces of the whole structure; and forming a third trench in the second trench downward, the third trench having a third depth greater than the second depth. The method of the present invention can make the whole trench have better etch uniformity, thereby obtaining good electrical performance.

3-stage method for forming deep trench structure and deep trench capacitor

A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method includes the steps of forming a first insulating layer that includes a nitride along a profile of a gate structure and a junction region, forming a temporary layer that has a doped oxide on the first insulting layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulting layer that has an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact ins the contact hole.

Method for forming self-aligned contact in semiconductor device

A bit line contact structure and fabrication method thereof. The method includes providing a substrate having a transistor, with a gate electrode, drain region, and source region, on the substrate, blanketly forming a first dielectric layer on the transistor using spin coating, and patterning the first dielectric layer, forming a via exposing the drain region.

Bit line contact structure and fabrication method thereof

Disclosed is a method for forming a bit line contact hole/contact structure. The method of the present invention includes steps of providing a substrate; forming a plurality of word line structures on the substrate; forming a doped dielectric layer on the substrate having the word line structures formed thereon; defining a position for forming a bit line contact hole; removing the doped dielectric layer other than the portion at the position for forming the bit line contact hole; forming a non-doped dielectric layer on the substrate having the word line structures and residual doped dielectric layer formed thereon; removing the residual doped dielectric layer by using an etchant with a high selectivity for doped dielectric layer/non-doped dielectric layer to form a bit line contact hole; and filling the bit line contact hole with conductive material to form a bit line contact structure.

Method for forming bit line contact hole/contact structure

A dual damascene process for producing interconnects. A dielectric layer is formed over the surface of a semiconductor substrate which comprises conductive layers or MOS devices. The dielectric layer is patterned to form trench openings and a metal layer is deposited over the dielectric layer to fill the plurality of trenches. A photoresist layer is formed over the metal layer and defined to form via hole patterns above the trenches. The metal layer and the dielectric layer are etched with the patterned photoresist layer as a mask to form a plurality of via holes exposing the underlying conductive layer or MOS devices and a dual damascene opening is formed.

Dual damascene process

A method for forming a contact opening is provided. After forming transistors on a substrate, a stacked resist layer including a resist layer without a silicon element and a resist layer with a silicon element covers the transistors and the substrate. The stacked resist layer is defined to cover a region of a contact opening to be formed as a mask. A selective growth process, such as a liquid phase oxide deposition (LPOD), is carried out to form a selective silicon oxide layer on the silicon-containing surface and fills the space between the stacked resist layer. After the stacked resist layer is removed, a contact opening is formed in the silicon oxide layer and a step of the etching process is eliminated.

Method for forming a contact opening

Method for forming bottle trenches by liquid phase oxide deposition. The method includes the steps of providing a substrate having a pad layer formed thereon, and a trench formed in a predetermined position; forming a masking layer at the bottom part of the trench; using liquid phase deposition (LPD) to form an LPD oxide layer on the sidewalls of the trench; removing the masking layer to expose the bottom part of the trench; subjecting the LPD oxide layer to annealing; and etching the bottom part of the trench not covered by the LPD oxide layer to form a bottle trench.

Growing community of inventors

Taoyuan, Taiwan

Meng-Hung Chen