Macronix International Co., Ltd.

Realtek Semiconductor Inc.

Meng Huang Liu

Tao Cheng Lu

Chun-Hsiang Lai

Xiang-Hua Shen

Dong Qiu

Sing Su

De-Pin Zheng

Chun Hsiang Lai

A chip verification system includes a plurality of agent modules, a register model, and a scoreboard module. The register model includes a register database, a plurality of access modules, and a return module. Each access module corresponds to one of a plurality of attribute parameters. Each agent module transmits an address code of its sequence to the return module. The return module obtains, according to the received address code, an address subject and the attribute parameter corresponding to the received address code from the register database, and outputs the obtained attribute parameter. Each driver module calls, according to the received attribute parameter, the corresponding access module to perform an operation on registers of DUT circuit according to a read write command of the sequence. The scoreboard module records each performed operation to generate an operation record, and outputs a verification result according to the operation record and data in registers.

Chip verification system and verification method therefor

An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage, so as to discharge the electrostatic charges. The anti-latch-up circuit has two terminals, which are respectively coupled to the voltage source and the ground voltage, and another connection terminal, used to send an anti-latch-up signal to the SCR for changing the activating rate. The latch-up phenomenon is avoided.

Electostatic discharge protection circuit coupled on I/O pad

Electrostatic discharge protection circuit coupled on I/O pad

The present invention provides an IC ESD cell, which is applicable to multiple-power-input and mixed-voltage ICs and capable of maintaining power sequence independence of each power source. The ESD cell of the present invention comprises a voltage selector circuit, which connects two separate power sources to select the one having a higher potential as the output voltage. An NMOS is used to connect the two separate power sources. An RC circuit is connected to an output of the voltage selector circuit to distinguish ESD event from normal power source. Therefore, the channel of the NMOS will be conducted to let the ESD current be led out via a designed path, hence preventing internal circuits of an IC from damage and accomplishing the object of whole chip protection.

Electrostatic discharge cell of integrated circuit

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Chu-Tung, Taiwan

Meng Huang Liu