Mediatek Corporation

Faraday Technology Corporation

Meng-Hsuan Wu

Yung-Hui Chung

Yen-Hsin Chu

A SAR ADC converting an analog signal into a digital signal having N bits counting from a most significant bit to a least significant bit includes a comparator comparing a positive component with a negative component of the analog signal, two CDACs and a logic circuit. For at least one i-th bit cycle of N bit cycle except a least significant bit cycle, one of a pair of capacitors relating to (i+1)-th bit respectively arranged in the two CDACs is switched according to a first comparing result of the comparator. After one of the pair of capacitors is switched, the comparator compares the positive component with the negative component of the analog signal again and generates a second comparing result. Then whether each one of capacitors relating to i-th bit in the two CDAC is to be switched is determined according to the first and the second comparing result.

Successive approximation register analog-digital converter and method for operating the same

A current providing system, for providing an output current, which comprises: a frequency detecting circuit, for receiving at least one input signal, and for detecting a frequency of the input signal; a frequency-controlled current providing circuit, for providing the output current according to the input signal frequency when the input signal frequency is in a first predetermined range; and a predetermined current providing circuit, for providing the output current with a first predetermined current value, when the input signal frequency is not in the first predetermined range.

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Taipei, Taiwan

Meng-Hsuan Wu