Rexchip Electronics Corporation

Meng-Hsien Chen

Chih-Wei Hsiung

Chung-Yung Ai

Yoshinori Tanaka

Wei-Che Chang

Kazuaki Takesako

Wei-Chih Liu

Chun-Chiao Tseng

Yukihiro Nagai

Yu-Ling Huang

Hirotake Fujita

Tomohiro Kadoya

Hsuan-Yu Fang

Yu-Shan Hsu

Chun-Hua Huang

Chih-Yuan Chen

Wen Kuei Hsu

Wen-Kuei Hsu

A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.

Semiconductor device and method for making the same

A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor.

Method for fabricating a vertical transistor

A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.

Self-aligned wet etching process

A three-dimensional dynamic random access memory with an ancillary electrode structure includes a substrate, at least one bit line formed on the substrate, at least one pillar element formed on a growth zone of the bit line, an ancillary electrode, a character line parallel with the substrate and perpendicular to the bit line, and at least one capacitor connecting to the pillar element. The bit line is formed on the substrate by doping and diffusing a doping element. The ancillary electrode is located on a separation zone of the bit line and adjacent to the pillar element. The character line is insulated from the ancillary electrode and incorporates with the bit line to output or input electronic data to the capacitor. Through the ancillary electrode, impedance of the bit line can be controlled to enhance conductivity of the bit line.

Three-dimensional dynamic random access memory with an ancillary electrode structure

Growing community of inventors

Taichung, Taiwan

Meng-Hsien Chen