Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Meng-Han Lin

Han-Jong Chia

Sai-Hooi Yeong

Sheng-Chen Wang

Yu-Ming Lin

Feng-Cheng Yang

Chia-En Huang

Chih-Ren Hsieh

Wei Cheng Wu

Te-Hsin Chiu

Te-An Chen

Chung-Te Lin

Yi-Ching Liu

Chi On Chui

Bo-Feng Young

Chen-Chin Liu

Chenchen Jacob Wang

Chih-Pin Huang

Chia-en Huang

Yong-Shiuan Tsair

Yih Wang

Chih-Yu Chang

Wen-Tuo Huang

Ching-Wen Chan

Kong-Beng Thei

Wei-Cheng Wu

Zhiqiang Wu

Chien-Chih Chou

Ya-Yun Cheng

Martin Liu

Peng-Chun Liou

Yu-Chien Chiu

Yung-Chang Chang

Yi-Huan Chen

Ya-Chen Kao

Li-Feng Teng

Chun-Fu Cheng

Chien-Hung Chang

Sai-hooi Yeong

Chia-Lin Liang

Meng-Sheng Chang

Mauricio Manfrini

Chih-Wen Hsiung

Chung-Wei Wu

Nuo Xu

Ya-Hui Wu

Feng-Ching Chu

Po-Tsun Liu

Han-Wei Wu

Chieh-Fang Chen

Chieh-Yi Shen

Wei-cheng Wu

Chun-fu Cheng

Tsung-Che Chiang

Zhen-Hao Li

Chieh-Chih Chou

Shih-Hsuan Chien

Zhen Yang

Chih-Hsuan Cheng

Hsin-Yi Huang

Chin Wen Chan

Chin-Wen Chan

A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a transistor coupled to a first capacitor and a second capacitor in series, respectively. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells, and wherein the logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first capacitor or second capacitor.

Back-end-of-line compatible physically unclonable function memory device and system

A semiconductor device includes a first and a second areas. The first area includes a plurality of first conductive stripes extending along a lateral direction and spaced from one another along a vertical direction, a first memory layer extending along the vertical direction, a first semiconductor layer extending along the vertical direction and coupled to a portion of the first memory layer, and second and third conductive stripes extending along the vertical direction, wherein the second and third conductive stripes are coupled to end portions of a sidewall of the first semiconductor layer. The second area includes a plurality of conductive sheets extending along the lateral direction and spaced from one another along the vertical direction, a second memory layer extending along the vertical direction and wrapped by the plurality of conductive sheets, and a second semiconductor layer extending along the vertical direction and wrapped by the second memory layer.

Memory devices and methods of manufacturing thereof

A semiconductor device includes a semiconductor substrate, first and second stack units disposed over the semiconductor substrate, and a feature disposed between the first and second stack units. Each of the first and second stack units includes at least one stack that includes a conductive film and a dielectric film stacked on each other. The feature includes a plurality of repeating units and a plurality of separators disposed to alternate with the repeating units. Each of the repeating units includes an inner portion including a pair of conductive pillars, and an outer portion including a memory film and a channel film. A method for manufacturing the semiconductor device is also disclosed.

Semiconductor memory device and method for manufacturing the same

In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Three-dimensional memory device and method

A semiconductor device includes a substrate, a metal gate and a poly gate. The substrate includes a first region and a second region. The metal gate is disposed on the first region of the substrate. The poly gate is disposed on the second region of the substrate. A gate area of the poly gate is greater than that of the metal gate.

Semiconductor device and method of forming the same

In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.

Semiconductor device with first and second source/drain epitaxial layers

A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.

Three-dimensional memory device and manufacturing method thereof

A device includes a word line, a dielectric layer, a gate dielectric layer, a semiconductive layer, a source line, and a memory stack. The word line is over a substrate. The dielectric layer is over the word line and has inner sidewalls over the word line. The gate dielectric layer is in contact with the word line and lines a top surface and inner sidewalls of the dielectric layer. The semiconductive layer is conformally over the gate dielectric layer. The semiconductive layer includes a source portion, a drain portion, and a channel portion. The source portion and the drain portion are over the top surface of the dielectric layer. The channel portion interconnects the source portion and the drain portion and in at a position lower than the source portion. The source line and the memory stack are respectively over the source portion and the drain portion.

Memory device and manufacturing method thereof

A semiconductor device includes a substrate, an active structure, a memory structure, and a first conductive line. The active structure is disposed on the substrate. The memory structure is disposed over the active structure, and has a lower surface and an upper surface opposite to each other. The memory structure includes a deep via disposed in the memory structure, and extends in an upward direction from the lower surface to terminate at the upper surface. The first conductive line is disposed above the upper surface of the memory structure, and extends in a first lengthwise direction transverse to the upward direction. The first conductive line is electrically connected to the active structure through the deep via. A method for manufacturing the semiconductor device is also disclosed.

Memory structure having novel circuit routing and method for manufacturing the same

A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

Systems and methods disclosed herein are related to a memory system. In one aspect, the memory system includes a first set of memory cells including a first string of memory cells and a second string of memory cells; and a first switch including: a first electrode connected to first electrodes of the first string of memory cells and first electrodes of the second string of memory cells, and a second electrode connected to a first global bit line, wherein gate electrodes of the first string of memory cells are connected to a first word line and gate electrodes of the second string of memory cells are connected to a second word line.

Using split word lines and switches for reducing capacitive loading on a memory system

In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

Three-dimensional memory devices

A ferroelectric memory device and a memory array are provided. The ferroelectric memory device includes a word line; a pair of source/drain electrodes, a channel layer, a work function layer and a ferroelectric layer. The source/drain electrodes are disposed at opposite sides of the word line, and elevated from the word line. The channel layer has a bottom planar portion and wall portions. The bottom planar portion extends along a top surface of the word line, and opposite ends of the bottom planar portion are connected to sidewalls of the source/drain electrodes through opposite ones of the wall portions. The work function layer is electrically connected to the word line, and extends along the bottom planar portion and the wall portions of the channel layer. The ferroelectric layer separates the channel layer from the work function layer.

Ferroelectric memory device and memory array

An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

Memory cell and method

A 3D memory array includes a tableland feature formed with multiple 3D memory sub-arrays that are arranged in an X-axis direction. Each 3D memory sub-array includes multiple memory cells that are distributed in multiple columns arranged in the X-axis direction, multiple bit lines extending in a Z-axis direction, multiple source lines extending in the Z-axis direction, and multiple word lines extending in a Y-axis direction. Each memory cell includes a first electrode, a second electrode and a gate electrode. Each bit line interconnects the first electrodes of some of the memory cells aligned in the Z-axis direction. Each bit line is electrically connected to another bit line of the same 3D memory sub-array, which is aligned with the bit line in the X-axis direction, and is electrically isolated from the bit lines of another 3D memory sub-array.

Structure of three-dimensional memory array

Growing community of inventors

Hsinchu, Taiwan

Meng-Han Lin