Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Meng-Han Lin

Han-Jong Chia

Sai-Hooi Yeong

Yu-Ming Lin

Sheng-Chen Wang

Feng-Cheng Yang

Chia-En Huang

Chih-Ren Hsieh

Wei Cheng Wu

Te-Hsin Chiu

Te-An Chen

Chung-Te Lin

Bo-Feng Young

Yi-Ching Liu

Chi On Chui

Chen-Chin Liu

Chenchen Jacob Wang

Chih-Pin Huang

Yong-Shiuan Tsair

Chia-en Huang

Yih Wang

Chih-Yu Chang

Wen-Tuo Huang

Ching-Wen Chan

Kong-Beng Thei

Wei-Cheng Wu

Zhiqiang Wu

Chien-Chih Chou

Ya-Yun Cheng

Martin Liu

Peng-Chun Liou

Yu-Chien Chiu

Yung-Chang Chang

Yi-Huan Chen

Ya-Chen Kao

Chun-Fu Cheng

Li-Feng Teng

Chien-Hung Chang

Chia-Lin Liang

Meng-Sheng Chang

Mauricio Manfrini

Chih-Wen Hsiung

Chung-Wei Wu

Nuo Xu

Ya-Hui Wu

Po-Tsun Liu

Han-Wei Wu

Sai-hooi Yeong

Chieh-Fang Chen

Chieh-Yi Shen

Wei-cheng Wu

Chun-fu Cheng

Chieh-Chih Chou

Tsung-Che Chiang

Zhen-Hao Li

Zhen Yang

Chin Wen Chan

Shih-Hsuan Chien

Chin-Wen Chan

Chih-Hsuan Cheng

Hsin-Yi Huang

A memory device includes a first memory array including: a plurality of memory strings spaced from each other along a first lateral direction and a second lateral direction, each of the plurality of memory strings including a plurality of memory cells arranged along a vertical direction; and a plurality of first conductive structures extending along the vertical direction; wherein each of the plurality of first conductive structures includes a first portion and a second portion; wherein the first portion extends across the plurality of memory cells of a corresponding pair of the plurality of memory strings along the vertical direction, and the second portion is disposed over the first portion along the vertical direction; and wherein the second portion extends farther than the first portion along at least one of the first or second lateral direction.

3D memory multi-stack connection method

A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

Transistor, memory device and manufacturing method of memory device

A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.

Method for forming a 3-D semiconductor memory structure comprising horizontal and vertical conductive lines

A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.

Method for improving control gate uniformity during manufacture of processors with embedded flash memory

A semiconductor device includes a first device over a substrate, wherein the first device includes a gate stack including a gate electrode material; a source/drain region in the substrate adjacent the gate stack; a first isolation region surrounding the gate stack; a gate contact over and contacting the gate stack, wherein the gate contact includes a gate contact material; and a second isolation region surrounding the gate contact; and a second device over the substrate, wherein the second device includes a first parallel capacitor including first electrodes, wherein the first electrodes include the gate electrode material, wherein the first isolation region separates the first electrodes; and a second parallel capacitor over the first parallel capacitor, wherein the second parallel capacitor includes second electrodes connected to the first electrodes, wherein the second electrodes include the gate contact material, wherein adjacent second electrodes are separated by the second isolation region.

Semiconductor device and method for forming capacitor structure

One aspect of this description relates to a semiconductor device. In some embodiments, the semiconductor device includes a first drain/source structure extending in a first direction, a second drain/source structure extending the first direction and spaced from the first drain/source structure in a second direction perpendicular to the first direction, a third drain/source structure extending in the first direction and spaced from the second drain/source structure in the second direction, a first bit line disposed over the first drain/source structure in the first direction, a common select line that includes a portion disposed over the second drain/source structure in the first direction, a second bit line disposed over the third drain/source structure in the first direction, and a charge storage layer coupled to at least a first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure.

Common-connection method in 3D memory

An integrated circuit device includes a substrate, an isolation feature, a memory cell, and a semiconductor device. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. The isolation feature is in the transition region. A top surface of the isolation feature has a first portion and a second portion lower than the first portion, the second portion of the top surface of the isolation feature is between the cell region and the first portion of the top surface of the isolation feature, and a bottom surface of the isolation feature has a step height directly below the second portion of the top surface of the isolation feature. The is memory cell over the cell region of the substrate. The semiconductor device is over the peripheral region of the substrate.

Integrated circuit device

Semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. The gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. A separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.

Semiconductor device and method of manufacturing

A memory device includes a plurality of first memory cells disposed along a vertical direction. Each of the plurality of first memory cells includes a portion of a first channel segment that extends along the vertical direction and has a first sidewall and a second sidewall. The first and second sidewalls of the first channel segment facing toward and away from a first lateral direction, respectively. Each of the plurality of first memory cells includes a portion of a first ferroelectric segment that also extends along the vertical direction and is in contact with the first sidewall of the first channel segment. A width of the first ferroelectric segment along a second lateral direction is different from a width of the first channel segment along the second lateral direction. The second lateral direction is perpendicular to the first lateral direction.

Three-dimensional ferroelectric memory device with width-differentiated channel and ferroelectric segments

A memory device, a semiconductor device and a manufacturing method of the memory device are provided. The memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. The first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. The third stacking structure is located between the first and second stacking structures. The first channel structure extends between the channel layers in the first and third stacking structures. The second channel structure extends between the channel layers in the second and third stacking structures. The gate dielectric layer and the first gate structure wrap around the first channel structure. The switching layer and the second gate structure wrap around the second channel structure.

Memory device, semiconductor device and manufacturing method of the memory device

A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Three-dimensional stackable ferroelectric random access memory devices and methods of forming

The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

Polysilicon resistor structures

A semiconductor device comprising a source, and a drain spaced apart from the source in a first direction. A channel layer is disposed radially outwards of at least one radially outer surface of the source and the drain in a second direction perpendicular to the first direction, the channel layer extending in the first direction. A memory layer is disposed on a radially outer surface of the channel layer in the second direction and extending in the first direction. A contact structure is interposed between the channel layer and at least a portion of the source and/or the drain, the contact structure having a lower resistance than the channel layer.

Semiconductor memory devices and methods of manufacturing thereof

A semiconductor device, comprises a source structure comprising an active source portion, an inactive source portion spaced apart from the active source portion in a vertical direction, and a first dielectric structure interposed between the active source portion and the inactive source portion. A drain structure is spaced apart from the source structure in a first direction. A channel layer is disposed on outer surfaces of the source and the drain structures. A memory layer is disposed on an outer surface of the channel layer so as to wrap around the channel layer. At least one gate layer is in electrical communication with the active source portion.

Semiconductor devices having a dielectric embedded in source and/or drain

A memory device includes a first memory cell. The first memory cell includes: a first conductor structure extending along a lateral direction; a first memory film comprising a first portion wrapping around a first portion of the first conductor structure; and a first semiconductor film wrapping around the first portion of the first memory film. A second conductor structure extends along a vertical direction and is coupled to a first end portion of the first semiconductor film along the lateral direction. A third conductor structure extends along the vertical direction and is coupled to a second end portion of the first semiconductor film along the lateral direction.

Semiconductor memory devices with wrapped word lines

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Hsinchu, Taiwan

Meng-Han Lin