Tsinghua University

Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Macronix International Co., Ltd.

National Yang Ming Chiao Tung University

Lite-on Technology Corporation

Lite-on Electronics (guangzhou) Limited

Meng-Fan Chang

Win-San Khwa

Jui-Jen Wu

Jen-Chieh Liu

Yi-Lun Lu

Tzu-Chiang Chen

Hung-Li Chiang

Jer-Fu Wang

Yen-Cheng Chiu

Cheng-Xin Xue

Shin-Jang Shen

Wei-Cheng Wu

Yu-Der Chih

Ku-Feng Lin

Shyh-Shyuan Sheu

Chien-Chen Lin

Ta-Wei Liu

Jian-Wei Su

Hiroyuki Yamauchi

Chien-Fu Chen

Ping-Chun Wu

Jia-Jing Chen

Jin Cai

Yen-Hsiang Huang

Wei-Hao Chen

Chieh-Pu Lo

Wen-Zhang Lin

Sheng-Po Huang

Albert Lee

Je-Syu Liu

Jin-Sheng Ren

Ming-Pin Chen

Li-Ya Lai

Xin Si

Chun-Hsiung Hung

Tung-Ying Lee

Xinyu Bao

Han-Wen Hu

Chia-Chi Liu

Yih-Shan Yang

Tsung-Hsien Huang

Yu-Lin Chen

Tsung-Yuan Huang

Elia Ambrosi

Pi-Feng Chiu

Tien-Fu Chen

Hui-Yao Kao

Che-Wei Wu

May-Be Chen

Yung-Ning Tu

Tzu-Hsien Yang

Keng-Hao Yang

Je-Min Hung

Jui Jen Wu

Ching-Hao Chuang

Li-Yang Hong

Fu-Chun Chang

Wei-Hsing Huang

Wei-Yu Lin

Huan-Ting Lin

Shou-Nan Hung

Yen-Chi Chou

Yao-Jen Kuo

Yen-Huei Chen

Chao-I Wu

Tung Ying Lee

Chien-Yuan Chen

Pei-Ling Tseng

Pei-Chia Chiang

Wen-Pin Lin

Yi-Ju Chen

Tzu-Hsiang Su

Chun-Ying Lee

Jen-Chien Fu

Chih-Cheng Hsieh

Ting-Wei Chang

Hon-Sum Philip Wong

Tung-Cheng Chang

Yi-Tse Hung

Kerem Akarvardar

Chih-He Lin

Pei-Yuan Li

Yu-Fan Lin

Kea-Tiong Tang

Zhe-Hui Lin

Ting-Hao Chang

Yen-Yao Wang

Hsien-Te Chen

Nai-Yin Sung

Yen-Chen Liu

Chia-Chen Kuo

Syuan-Hao Sie

Rawan Naous

Ru-Hui Liu

Shuai-Fan Chen

Chuan-Jia Jhang

Wei-Chang Zhao

Hsiang-Pan Li

Chia-Yin Li

Jui-Yu Hung

A memory system and operating method for controlling the same are provided. The memory system includes a memory array and a control circuit. The memory array comprising a first memory block and a second memory block, wherein the first memory block has a longer endurance than the second memory block. The control circuit is configured to receive a neural network model having a plurality of weight data; divide each of the plurality of weight data into a first data segment and a second data segment, wherein the first data segment has a higher bit order than the second data segment; and program the plurality of first data segments on the first memory block and program the plurality of second data segments on the second memory block.

Memory system and operating method of the same

Memory circuits that read the bit state of memory cells are disclosed. In some embodiments, a memory circuit, includes a memory cell configured to store a bit. A reference line is configured to receive a reference signal and a data line is configured to receive a data signal. The data line is configured to be selectively coupled to the memory cell. A charge voltage select unit is configured to charge the reference line and the data line in response to a select signal being in a first select state and discharge the reference line and the data line in response to the select signal being in a second select state. A sense amplifier is configured to compare the data signal and the reference signal to sense a bit state of the bit stored by the memory cell.

Systems and methods for reading bit state in arrays of memory cells

A memory device includes a current source and a memory array. The current source is configured to provide a current to a first node. The memory array is coupled to the current source at the first node. The memory array includes memory cells. First terminals of the memory cells are coupled to the first node. Each of the memory cells has a first resistance in response to having a first data value, and has a second resistance in response to having a second data value. The second data value is N times the first data value. The second resistance is approximately one-Nth of the first resistance, for N being a positive integer larger than one. A method of operating a memory device is also disclosed herein.

Memory device and operating method thereof

A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.

Control circuit, memory system and control method

An input sequence re-ordering method with a multi input-precision reconfigurable scheme and a pipeline scheme for a computing-in-memory macro in a convolutional neural network application is configured to re-order a plurality of multi-bit input signals and includes performing a scanning step and a re-ordering step. The scanning step includes driving a scanner to scan one group of the multi-bit input signals to determine whether an initial value of a plurality of flag signals in one of a plurality of multi-bit section flags is changed to an inverted initial value according to a plurality of bit numbers of the one group of the multi-bit input signals. The re-ordering step includes driving a sorter to select a part of the one group of the multi-bit input signals corresponding to a plurality of the inverted initial values of the flag signals in the one of the multi-bit section flags.

Input sequence re-ordering method and input sequence re-ordering unit with multi input-precision reconfigurable scheme and pipeline scheme for computing-in-memory macro in convolutional neural network application

An integrated circuit device includes a first bit line structure that has a horizontal portion and a vertical portion in which an upper surface of the vertical portion is exposed for making electrical contact with a contact that, in turn, is in electrical contact with a metal pattern through which operating voltages may be applied to the bit line structure.

Self-aligned contact for embedded memory

A memory device includes a transistor and a memory cell. The transistor includes a gate electrode disposed over a substrate and source/drain regions in the substrate beside the gate electrode. The memory cell is disposed over the transistor and includes a bottom electrode electrically connected to one of the source/drain regions, a top electrode disposed over the bottom electrode, and a first bit and a second bit separated from each other and disposed between the bottom electrode and the top electrode.

Memory devices and methods of forming the same

A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.

3T memory with enhanced speed of operation and data retention

A dynamic differential-reference time-to-digital converter for computing-in-memory applications is controlled by a bias reference and a predetermined setting parameter, and includes a configurable main-reference selector and a plurality of time-to-digital converters. The configurable main-reference selector is configured to receive a plurality of edge-output signals, select one of the edge-output signals as a main reference and select others of the edge-output signals as a plurality of edge selected signals according to the predetermined setting parameter. One of the time-to-digital converters is configured to compare the bias reference with the main reference to output a bias multiplication-and-accumulation value, and others of the time-to-digital converters are configured to compare the main reference with the edge selected signals to output a plurality of differential multiplication-and-accumulation values. The bias multiplication-and-accumulation value and the differential multiplication-and-accumulation values are dynamically adjusted according to the bias reference and the predetermined setting parameter.

Memory array structure with dynamic differential-reference based readout scheme for computing-in-memory applications, dynamic differential-reference time-to-digital converter for computing-in-memory applications and computing method thereof

A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.

Memory test circuit, memory chip, and testing method of memory chip

The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.

Shift register having low power mode

A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.

SRAM memory cell device comprising ferroelectric access and storage transistors

A circuit includes first and second data lines, a sense amplifier including first and second input terminals, a first p-type metal-oxide-semiconductor (PMOS) transistor coupled in series with a first capacitive device between the first data line and the second input terminal, a second PMOS transistor coupled in series with a second capacitive device between the second data line and the first input terminal, a third PMOS transistor coupled between the first data line and the first input terminal, a fourth PMOS transistor coupled between the second data line and the second input terminal, a first n-type metal-oxide-semiconductor (NMOS) transistor configured to selectively couple each of the first PMOS transistor and the first capacitive device to a ground node, and a second NMOS transistor configured to selectively couple each of the second PMOS transistor and the second capacitive device to the ground node.

Sense amplifier circuit and method

A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

Memory devices, circuits and methods of adjusting a sensing current for the memory device

An integrated circuit includes a memory storage having bit cells, a write path switch configured to have a connection state determined by a reliability indicator, and a write driver having an input configured to receive an input data from a write terminal through either a first write path or a second write path. The input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal. The reliability indicator is configured to be set based on a majority bit value in the data or based on a minority bit value in the data.

Non-volatile memory stored with encoded data

Growing community of inventors

Taichung, Taiwan

Meng-Fan Chang