Industrial Technology Research Institute

Via Technologies, Inc.

Meng-Da Yang

An-Yeu Wu

Murphy Chen

A predicted parallel branch slicer for use in an adaptive decision feedback equalizer includes Madders commonly receiving a signal to be processed and respectively receiving Mpreset values, and performing respective addition operations to generate Moutput signals; Mslicers in communication with the Madders, receiving and processing the Moutput signals to obtain Msignals of Mlevels, respectively; a multiplexer in communication with the Mslicers, receiving the signals of the Mlevels; and k delay units interconnected with one another in series and being in communication with the multiplexer, and generating k selection signals of different delay time in response to an output of the multiplexer, the selection signals being provided for the multiplexer to select one of the signals of the Mlevels to be outputted.

Predicted parallel branch slicer and slicing method thereof

A fast convergent pipeline adaptive decision feedback equalizer using a post-cursor processing filter is disclosed, which includes a feed-forward equalizer, a post-cursor processing filter, an adder, a slicer, a register, a pipelined feedback equalizer, a subtractor and a updating device. The pipelined feedback equalizer has a delay device coupled to the register for delaying its output signal, and a feedback equalizer coupled to the delay device for eliminating the post-cursor of the output signal. By using the post-cursor processing filter (PCF), it increases the operating clock rate with arbitrary speedup factor, and improves the convergence rate of the overall system.

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Miaoli, Taiwan

Meng-Da Yang