Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Realtek Semiconductor Inc.

Via Technologies, Inc.

Meng-Chun Chang

Clement Hsingjen Wann

Neng-Kuo Chen

Sey-Ping Sun

Gin-Chen Huang

Sung-Li Wang

Chih-Hsin Ko

Yu-Lien Huang

Ding-Kang Shih

Yi-An Lin

Chen-Feng Hsu

Hau-Yu Lin

Ling-Yen Yeh

Chi-Yuan Shih

Li-Chi Yu

Chin-Hsiang Lin

Chun Hsiung Tsai

Yen-Chun Huang

Ta-Chun Ma

Chi-Wen Liu

Huan-Just Lin

Chia-Ying Lee

Ting-Chu Ko

Chung-Hsien Chen

Hong-Jie Yang

Meng Jhe Tsai

Hao Chiang

Chuan Chang

Yih-Shen Chen

Yasutoshi Okuno

Chien-Wen Chen

Yi-Fang Pai

Yusuke Oniki

Yi-Ting Wang

Chia-Chi Huang

Chorng-Ren Sheu

Cheng-Long Chen

Chung-Ju Chang

Jia-Ching Shen

Yung-Han Chen

Yu-Jung Chang

Chih-Yu Chen

Hung-Wen Yu

A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Fin field-effect transistor device and method

A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.

Semiconductor device and a method for fabricating the same

A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Wrap-around contact on FinFET

A feedforward echo cancellation device includes: a first impedance circuit for responding to a transmission current to output a first current to a node; an echo cancellation current generating circuit for drawing an echo cancellation current from the node; a circuit module that is coupled to the echo cancellation current generating circuit and the node has a first impedance value adjusted based on a system convergence index of a communication device, where the first impedance value is used to determine a gain of a programmable gain amplifier in the communication device; and a second impedance circuit for responding to the transmission current to output a second current to the node, where a second impedance value of the second impedance circuit is adjusted based on the first impedance value of the circuit module accordingly. Specifically, the node is coupled to an input terminal of the programmable gain amplifier.

Feedforward echo cancellation device

A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

Self-aligned dual-metal silicide and germanide formation

A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.

Semiconductor structure with enhanced contact and method of manufacture the same

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Taipei, Taiwan

Meng-Chun Chang