Arm Finance Overseas Limited

Nvidia Corporation

Mediatek Corporation

Mips Technologies, Inc.

Meng-Bing Yu

Era Kasturia Nangia

Michael Ni

Vidya Rajagopalan

Karagada Ramarao Kishore

Dz-Ching Ju

Yun-Ching Li

A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to The particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.

Load/store unit for a processor, and applications thereof

A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

Data cache virtual hint way prediction, and applications thereof

In one embodiment, a microprocessor is provided. The microprocessor includes a cache that is controlled by a cache controller. The cache controller is configured to replace cachelines in the cache based on a replacement scheme that prioritizes the replacement of cachelines that are less likely to cause roll back of a transaction of the microprocessor.

Cache control to reduce transaction roll back

A memory management method includes: checking shared virtual memory (SVM) support ability of at least one device participating in data access of a buffer; referring to a checking result to adaptively select an SVM mode; and allocating the buffer in a physical memory region of a memory device, and configuring the buffer to operate in the selected SVM mode.

Memory management method for supporting shared virtual memories with hybrid page table utilization and related machine readable medium

A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to the particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.

Growing community of inventors

San Jose, CA, United States of America

Meng-Bing Yu