Tower Semiconductor Ltd.

Ramot at Tel-aviv University Ltd.

Menachem Vofsy

Yakov Roizin

Alexey Heiman

Yossi Rosenwaks

Efraim Aloni

Micha Gutman

Klimentiy Shimanovich

Yhonatan Vaknin

Avi Ben-Gigi

Zohar Shaked

Koji Yoshida

Masatoshi Arai

Fumihiko Noro

Nobuyoshi Takahashi

For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

Apparatus, system and method of an electrostatically formed nanowire (EFN)

Some demonstrative embodiments include an apparatus of a temperature sensor to sense temperature, the apparatus including a first pad on a silicon substrate; a second pad on the silicon substrate; a silicon nanowire having a first end coupled to the first pad and a second end coupled to the second pad, the silicon nanowire configured to drive a current between the first pad and the second pad, the current depending at least on the temperature; and a charged dielectric layer covering at least three sides of the silicon nanowire.

Apparatus, system and method of a temperature sensor

A CMOS gas sensor that uses MTJ elements to capture/store gas concentration level data at high temperatures for later readout at low temperatures. Each MTJ element includes a storage layer whose magnetic orientation is switchable between parallel and anti-parallel directions relative to a fixed reference when heated above the storage layer's blocking temperature, whereby the MTJ element is switchable between low and high resistance states. During operation, reaction heat generated by a gas sensing element raises the MTJ element's temperature above the blocking temperature when ambient target gas exceeds a minimum concentration level, whereby an applied magnetic biasing force causes the storage layer's magnetic orientation to switch relative to the fixed reference, whereby the MTJ element captures measured concentration level data for later readout. In one embodiment, multiple MTJ elements connected in a NAND-type string switch at different concentration levels to provide highly accurate quantitative measurement data.

Semiconductor gas sensor using magnetic tunnel junction elements

Gas sensing using MTJ elements to capture/store gas concentration level data for readout at room temperature. In one embodiment, during reset the MTJ elements are heated above blocking temperatures of their storage layers while applying a first magnetic biasing force to set initial magnetic orientations. During gas sensing, reaction heat from a gas sensing element combines with control heat to raise each MTJ element's temperature from a work point temperature above its blocking temperature only when the target gas exceeds an associated concentration level, whereby a second magnetic biasing force causes the magnetic orientation to switch directions. During readout, read currents are measured to determine the MTJ elements' final resistance states, which indicate their switched/non-switched states, and the resistance states are correlated with stored data to determine the measured gas concentration level. The MTJ elements are cooled after reset and gas sensing to facilitate accurate CDS readout data.

Gas sensing using magnetic tunnel junction elements

A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.

Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories

A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.

Growing community of inventors

Kiriat Tivon, Israel

Menachem Vofsy