Intel Corporation

Men Long

David M Durham

Siddhartha Chhabra

Alpa T Narendra Trivedi

Uday R Savagaonkar

Hormuzd M Khosravi

Prashant Dewan

Karanvir S Grewal

Eugene M Kishinevsky

Michael Lemay

Manoj R Sastry

Uri Blumenthal

Kirk S Yap

Baiju V Patel

Jesse R Walker

Carlos Ornelas

Edgar Borrayo

Carlos V Rozas

Yasser Rasheed

Venkat R Gokulrangan

Ravi L Sahita

Alpa Narendra Trivedi

Xiaozhu Kang

Divya Naidu Kolar Sunder

Jungju Oh

Ram K Krishnamurthy

Ioannis T Schoinas

Eliezer Tamir

Niranjan L Cooray

Sergej Deutsch

Robert W Strong

James T Doyle

Lokpraveen B Mosur

Nicholas D Triantafillou

Patrick Koeberl

Paritosh Saxena

Vincent Edward Von Bokern

Simoni Ben-Michael

Farhana Sheikh

Stanley Steve Kulick

Binata Bhattacharyya

Paul J Thadikaran

Ramadass Nagarajan

Hossein Alavi

David A Edwards

Akshay Ramesh Kadam

Paul S Schmitz

Edward J Pullin

Robert J Toepfer

Steven D Williams

Richard J Heiler

Divya Naidu Kolar Sundar

Evgeny Zhyvov

Brad W Stewart

Carol L Barrett

Marc Millier

Lemay Michael

Durham David M

Encryption interface technologies are described. A processor can include a system agent, an encryption interface, and a memory controller. The system agent can communicate data with a hardware functional block. The encryption interface can be coupled between the system agent and a memory controller. The encryption interface can receive a plaintext request from the system agent, encrypt the plaintext request to obtain an encrypted request, and communicate the encrypted request to the memory controller. The memory controller can communicate the encrypted request to a main memory of the computing device.

Encryption interface

Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.

Security plugin for a system-on-a-chip platform

Technologies for execute only transactional memory include a computing device with a processor and a memory. The processor includes an instruction translation lookaside buffer (iTLB) and a data translation lookaside buffer (dTLB). In response to a page miss, the processor determines whether a page physical address is within an execute only transactional (XOT) range of the memory. If within the XOT range, the processor may populate the iTLB with the page physical address and prevent the dTLB from being populated with the page physical address. In response to an asynchronous change of control flow such as an interrupt, the processor determines whether a last iTLB translation is within the XOT range. If within the XOT range, the processor clears or otherwise secures the processor register state. The processor ensures that an XOT range starts execution at an authorized entry point. Other embodiments are described and claimed.

Technologies for execute only transactional memory

An example apparatus includes a scan manager to add a portion of a page of physical memory from a first sequence of mappings to a second sequence of mappings in response to determining the second sequence includes an address corresponding to the portion of the page of physical memory, and a scanner to scan the first sequence and the second sequence to determine whether at least one of first data in the first sequence or second data in the second sequence includes a pattern indicative of malware.

Memory scanning methods and apparatus

Memory scanning methods and apparatus are disclosed. An example apparatus includes an address identifier to, when an entry of a paging structure has been accessed, determine a first address corresponding to a page of physical memory when the entry of the paging structure maps to the page of the physical memory; and a scanner to: scan a threshold amount of memory beginning at a physical memory address corresponding to the first address; and determine whether the threshold amount of memory includes a pattern indicative of malware.

Memory scanning methods and apparatus are disclosed. An example apparatus includes scan manager to identify a physical memory address that has recently been accessed. The physical memory address is identified as having been recently accessed when an access has occurred within a threshold of a current time. The apparatus also includes a scanner to scan a threshold amount of memory beginning at the physical memory address, and determine whether the memory included in the threshold amount of memory includes a pattern indicative of malware.

Embodiments of the invention include a machine-readable medium having stored thereon instructions, which if performed by a machine causes the machine to perform a method that includes assigning an urgency of requests based on a priority level for incoming requests and associated entries in at least one priority queue, assigning an urgency delta for anti-starvation that indicates urgency promotion to prevent starvation for the incoming requests in the at least one priority queue, determining conflict information including whether an incoming request is dependent on any request already present in the at least one queue, determining all contending requests within the at least one priority queue during a cycle, and sending a selected contending request to a memory controller for accessing memory.

Urgency based reordering for priority order servicing of memory requests

Technologies for memory encryption include a computing device to generate a keyed hash of a data line based on a statistical counter value and a memory address to which to write the data line and to store the keyed hash to a cache line. The statistical counter value has a reference probability of incrementing at each write operation. The cache line includes a plurality of keyed hashes and each of the keyed hashes corresponds with a different data line. The computing device further encrypts the data line based on the keyed hash, the memory address, and the statistical counter value.

Technologies for memory confidentiality, integrity, and replay protection

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Beaverton, OR, United States of America

Men Long