International Business Machines Corporation

Men-Chow Chiang

Hong Lam Hua

Robert H Bell, Jr

Mysore Sathyanaranyana Srinivas

Sujatha Kashyap

Ken Van Vu

Mathew Accapadi

Mysore Sathyanarayana Srinivas

Kiet Hien Lam

Kaivalya M Dixit

Techniques for preserving memory affinity in a computer system is disclosed. In response to a request for memory access to a page within a memory affinity domain, a determination is made if the request is initiated by a processor associated with the memory affinity domain. If the request is not initiated by a processor associated with the memory affinity domain, a determination is made if there is a page ID match with an entry within a page migration tracking module associated with the memory affinity domain. If there is no page ID match, an entry is selected within the page migration tracking module to be updated with a new page ID and a new memory affinity ID. If there is a page ID match, then another determination is made whether or not there is a memory affinity ID match with the entry with the page ID field match. If there is no memory affinity ID match, the entry is updated with a new memory affinity ID; and if there is a memory affinity ID match, an access counter of the entry is incremented.

Technique for preserving memory affinity in a non-uniform memory access data processing system

According to one aspect of the present disclosure, a method and technique for performance-driven cache line memory access is disclosed. The method includes: receiving, by a memory controller of a data processing system, a request for a cache line; dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; servicing the high priority data request; and delaying servicing of the low priority data request until a low priority condition has been satisfied.

Performance-driven cache line memory access

According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving, a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied.

A method, system and computer-usable medium are disclosed for a lock-spin-wait operation for managing multi-threaded applications in a multi-core computing environment. A target processor core, referred to as a 'spin-wait core' (SWC), is assigned (or reserved) for primarily running spin-waiting threads. Threads operating in the multi-core computing environment that are identified as spin-waiting are then moved to a run queue associated with the SWC to acquire a lock. The spin-waiting threads are then allocated a lock response time that is less than the default lock response time of the operating system (OS) associated with the SWC. If a spin-waiting fails to acquire a lock within the allocated lock response time, the SWC is relinquished, ceding its availability for other spin-waiting threads in the run queue to acquire a lock. Once a spin-waiting thread acquires a lock, it is migrated to its original, or an available, processor core.

Lock spin wait operation for multi-threaded applications in a multi-core computing environment

A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD.

Hybrid storage subsystem with mixed placement of file contents

A method for minimizing cache conflict misses is disclosed. A translation table capable of facilitating the translation of a virtual address to a real address during a cache access is provided. The translation table includes multiple entries, and each entry of the translation table includes a page number field and a hash value field. A hash value is generated from a first group of bits within a virtual address, and the hash value is stored in the hash value field of an entry within the translation table. In response to a match on the entry within the translation table during a cache access, the hash value of the matched entry is retrieved from the translation table, and the hash value is concatenated with a second group of bits within the virtual address to form a set of indexing bits to index into a cache set.

Method and apparatus for minimizing cache conflict misses

An operating system of an information handling system (IHS) determines a process tree of data sharing threads in an application that the IHS executes. A load balancing manager assigns a home processor to each thread of the executing application process tree and dispatches the process tree to the home processor. The load balancing manager determines whether a particular poaching processor of a virtual or real processor group is available to execute threads of the executing application within the home processor of a processor group. If ready or run queues of a prospective poaching processor are empty, the load balancing manager may move or poach a thread or threads from the home processor ready queue to the ready queue of the prospective poaching processor. The poaching processor executes the poached threads to provide load balancing to the information handling system (IHS).

Processor thread load balancing manager

A processor thread load balancing manager employs an operating system of an information handling system (IHS) that determines a process tree of data sharing threads in an application that the IHS executes. The load balancing manager assigns a home processor to each thread of the executing application process tree and dispatches the process tree to the home processor. The load balancing manager determines whether a particular poaching processor of a virtual or real processor group is available to execute threads of the executing application within the home processor of a processor group. If ready or run queues of a prospective poaching processor are empty, the load balancing manager may move or poach a thread or threads from the home processor ready queue to the ready queue of the prospective poaching processor. The poaching processor executes the poached threads to provide load balancing to the information handling system (IHS).

A system and method for allowing jobs originating from different partitions to simultaneously utilize different hardware threads on a processor by concatenating partition identifiers with virtual page identifiers within a processor's translation lookaside buffer is presented. The device includes a translation lookaside buffer that translates concatenated virtual addresses to system-wide real addresses. The device generates concatenated virtual addresses using a partition identifier, which corresponds to a job's originating partition, and a virtual page identifier, which corresponds to the executing instruction, such as an instruction address or data address. In turn, each concatenated virtual address is different, which translates in the translation lookaside buffer to a unique system-wide real address. As such, jobs originating from different partitions are able to simultaneously execute on the device and, therefore, fully utilize each of the device's hardware threads.

System and method for enabling micro-partitioning in a multi-threaded processor

Mechanisms for reducing memory overhead of a page table in a dynamic logical partitioning (LPAR) environment are provided. Each LPAR, upon its creation, is allowed to declare any maximum main memory size for the LPAR as long as the aggregate maximum main memory size for all LPARs does not exceed the total amount of available main memory. A single page table is used for all of the LPARs. Thus, the only page table in the computing system is shared by all LPARs and every memory access operation from any LPAR must go through the same page table for address translation. As a result, since only one page table is utilized, and the aggregate size of the main memory apportioned to each of the LPARs is limited to the size of the main memory, the size of the page table cannot exceed the size of the main memory.

Reducing memory overhead of a page table in a dynamic logical partitioning environment

A control mechanism that allows individual applications to turn hardware prefetch on or off is provided. By preliminary trial run one can determine precisely whether an application will benefit or suffer from hardware prefetch. The selective control of prefetching by individual applications is made possible by associating a status bit with individual processes in the machine status word of each processor. Using this prefetch bit, a process turns prefetching on or off to its own advantage in the processor core immediately after a context switch.

Runtime selective control of hardware prefetch mechanism

A mechanism for generating pre-translated segments for use in virtual to real address translation is provided in which segments that are determined to meet a density threshold are promoted to a pre-translated segment class. The pages of these segments are moved to a contiguous portion of memory and the segment table entry corresponding to the segment is updated to indicate the segment to be a pre-translated segment and to include the base real address for the contiguous portion of memory. In one embodiment, as each page is moved, its page table entry is updated to point to the new location of the page so that the page is still accessible during promotion of the segment to a pre-translated segment. In this way, virtual-to-real address translation may be performed by concatenating the segment base real address, the page identifier, and a byte offset into the page.

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Austin, TX, United States of America

Men-Chow Chiang