Texas Instruments Corporation

Raytheon Company

Men-Chee Chen

Cetin Kaya

Freidoon Mehrad

Malcolm John Bevan

Reima Tapani Laaksonen

Daty Michael Rogers

The invention comprises a floating gate memory structure, a method for making a floating gate memory structure, and a method for forming a continuous source line in a floating gate memory structure. One aspect of the invention is a method for forming a continuous source line. A plurality of trenches and moats are formed in a semiconductor structure wherein the moats are adjacent to the trenches. A portion of each moat forms the source region of a transistor. A silicate glass layer is deposited outwardly from a semiconductor structure to form an intermediate structure. The silicate glass layer contains an n-type dopant. The intermediate structure is heated for a first period of time to dope the plurality of trenches. Portions of the doped plurality of trenches form a part of at least one continuous source line.

Floating gate memory structure and method for forming a low resistance continuous source line

A method of forming a floating gate memory device having a memory array region (11), a first periphery region (15), and a second periphery region (17) is provided that comprises forming a polysilicon gate (18) insulatively disposed outwardly from a substrate (10) in the memory array region (11). The polysilicon gate (18) is doped with nitrogen ions. A first oxide layer (20) is formed outwardly from the substrate (10) in the first and second periphery regions (15) and (17) and from the polysilicon gate (18) of the memory array region (11). The thickness of oxide formed outwardly from the substrate (10) is greater relative to the thickness of oxide formed outwardly from the polysilicon gate (18). The first oxide layer (20) in the second periphery region (17) is removed. A second oxide layer (22) is formed outwardly from the substrate (10) of the second periphery region (13), from the first oxide layer (20) in the first periphery region (15) and from the polysilicon gate (18) of the memory array region (11). The thickness of the second oxide layer (22) formed in the first and second periphery regions (15) and (17) is greater relative to the thickness of oxide formed in the memory array region (11).

System and method for forming an inter-layer dielectric in floating gate

A method of forming a floating gate memory array is provided that uses a two step etch process to prevent the formation of unwanted trenches 66 into the semiconductor substrate 26. The process may be accomplished by a first etch which is substantially not selective between silicon and dielectric materials. A second etch process is then used which is highly selective to dielectric materials.

Stack etch method for flash memory devices

A room temperature emitter (10) operating in the 3-5 .mu.m wavelength range is provided. The emitter (10) includes a substrate (12) formed of a material selected from the group comprising cadmium telluride or cadmium zinc telluride. An epitaxial active layer (14) is formed over the substrate (12) from mercury cadmium telluride. The active layer (14) may be either a p-type or an n-type layer. The active layer (14) is doped with a predetermined concentration of dopant selected from the group comprising indium and arsenic. More particularly, if the active layer (14) is a p-type layer, it is doped with arsenic in a concentration between approximately 1.times.10.sup.16 atoms/cm.sup.3 and 1.times.10.sup.17 atoms/cm.sup.3. If the active layer (14) is an n-type layer, it is doped with indium in a concentration between approximately 5.times.10.sup.14 atoms/cm.sup.3 to 1.times.10.sup.15 atoms/cm.sup.3. A first epitaxial confinement layer (16) is formed from mercury cadmium telluride. The first confinement layer (16) is formed over the active layer (14). The first confinement layer (16) may be either an n.sup.+ layer or a p.sup.+ layer, depending upon whether the active layer (14) is a p-type or n-type layer. A metal layer (18) is formed over the first confinement layer (16).

Room temperature 3-5 micrometer wavelength HgCdTe heterojunction emitter

A system and method for testing the properties of semiconductor material including an enclosed chamber, a sample of semiconductor material under test having a polished surface portion and insulator layer over the polished surface portion supported in the chamber, a spring probe disposed within the chamber impinging against the insulator layer, a contact disposed on a surface portion of the semiconductor material under test, a pair of contacts disposed external to the chamber, each of the pair of contacts coupled to a different one of the contact and the spring probe and a container supporting the chamber and containing a cryogenic material therein surrounding the chamber. The semiconductor material is preferably a group II-VI composition, preferably HgCdTe. The contact disposed on the surface portion of the semiconductor material is preferably indium. A support, preferably sapphire, is provided for the sample. In a second embodiment, the support for the material under test is controllable for movement in a plane normal to the probe.

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Dallas, TX, United States of America

Men-Chee Chen