Burroughs, Inc.

Unisys Corporation

Melvyn E Genter

Hanan Potash

Bruce B Roesner

Burton L Levin

A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consists essentially of a single element semiconductor selected from the group of Si, Ge, C, and .alpha.-Sn, having a crystalline grain size which is smaller than polycrystalline. Dopant atoms in the semiconductor are limited to be less than 10.sup.17 atoms/CM.sup.3 ; and, such a doping range includes zero doping. All dopant atoms are interstitial in the semiconductor crystals and not substitutional.

Electrically alterable resistive component stacked above a semiconductor

In the disclosed computer, a plurality of register means for storing digital operands and control signals are in a semiconductor substrate; an arithmetic means for performing functional opertions on the operands are also in the substrate; an insulating layer covers the register means and the arithmetic means; and an interconnect matrix is on top of this insulating layer. The interconnect matrix includes pluralities of logic gates coupled through the insulating layer to the register means and arithmetic means and selectively interconnects them in response to the control signals.

Digital computer having an interconnect mechanism stacked above a

Disclosed is a data processing system which is comprised of a plurality of devices that carry on conversations with each other over a time-shared bus. These conversions can consist of a message from a device A to a device B which is immediately followed by a message from device B back to device A, or a message from device A to device B which is immediately followed by a message from device B to another device C, or a single message from device A to device B. In each case, the last device to receive a message assumes control of the bus; and it relinquishes this control by either sending a message to another device or by broadcasting a poll code to all devices on the bus.

Method of operating a bus in a data processing system via a repetitive

A flexible architecture for digital computers can be adapted to meet the many different functional requirements of several computer models. Each model includes an array of sequential logic units. These units include respective control memories for storing commands, means for sequentially fetching and executing selectable sequences of the commands, and soft functional structures for performing customized functions in response to the commands. Included within the soft functional structures are a plurality of selectable electrical contacts which customize the functional response of the structures to the commands. Except for these contacts and the content of the respective control memories, the units are substantially identical. All of the units in the array execute respective command sequences from their control memory to perform a single instruction for the computer model.

Flexible computer architecture using arrays of standardized

Disclosed is a digital device on a semiconductor chip, which is comprised of a plurality of storage means for storing digital signals therein, a plurality of functional means for performing functional operations on the digital signals, and an interconnect matrix. The matrix includes a plurality of input busses connected to receive signals from the storage means and the functional means, and a plurality of output busses connected to send signals to the storage means and functional means. The interconnect matrix further includes N sets of selectable electrical contacts where N is any positive integer. Each set selectively intercouples the input busses to the output busses in various parallel paths. Signals are transferred between the input and output busses through any one set of the N sets of electrical contacts in response to N respective control signals.

Growing community of inventors

San Diego, CA, United States of America

Melvyn E Genter