Freescale Semiconductor,inc.

Motorola Corporation

Melvy Freeland Miller, Iii

Lianjun Liu

Peter Zurcher

Sriram Kalpat

Thomas P Remmel

Qiang Li

Juergen A Foerstner

Sergio P Pacheco

Daniel N Koury, Jr

Jeffrey A Dykstra

Thuy B Dao

A toroidal inductor formed in a semiconductor substrate. Through-silicon vias are used to connect metal layers formed on top and bottom surfaces of the semiconductor substrate. In one embodiment, the vias are elongated and laid out in two concentric circles, an inner circle enclosed by an outer circle. The vias of the outer concentric circle are longer than the vias of the inner circle so that spaces between vias are the same for both circles. In another embodiment, each elongated via may include a plurality of circular vias formed in a line. Metals layers on the top and bottom of the semiconductor substrate are patterned to form wedge shaped connectors between the inner and outer vias to form the spirals of the toroidal inductor. The wedge shaped connectors with elongated vias allow spacing between spirals to be constant.

Method for forming a toroidal inductor in a semiconductor substrate

A MEMS capacitive device () includes a fixed capacitor plate () formed on a surface () of a substrate (). A movable capacitor plate () is suspended above the fixed capacitor plate () by compliant members () anchored to the surface (). A movable element () is positioned in spaced apart relationship from the movable capacitor plate () and has an actuator () formed thereon. Actuation of the actuator () causes abutment of a portion of the movable element () against a contact surface () of the movable plate (). The abutment moves the movable plate () toward the fixed plate () to alter a capacitance () between the plates (). Another substrate () may be coupled to the substrate () such that a surface () of the substrate () faces the surface () of the substrate (). The movable element () may be formed on the surface ().

MEMS capacitive device and method of forming same

A method of making a semiconductor device includes the steps of: providing a semiconductor substrate () having a patterned interconnect layer () formed thereon; depositing a first dielectric material () over the interconnect layer; depositing a first electrode material () over the first dielectric material; depositing a second dielectric material () over the first electrode material; depositing a second electrode material () over the second dielectric material; patterning the second electrode material to form a top electrode () of a first capacitor (); and patterning the first electrode material to form a top electrode () of a second capacitor (), to form an electrode () of the first capacitor, and to define a resistor ().

Semiconductor device comprising passive components

A microelectromechanical systems (MEMS) componentincludes a portionof a MEMS structureformed on a semiconductor substrateand a portionof the structureformed in a non-semiconductor substrate. The non-semiconductor substrateis in fixed communication with the semiconductor substratewith the portionof the MEMS structurebeing interposed between the substratesand. A fabrication methodentails utilizing semiconductor thin-film processing techniques to form the portionon the semiconductor substrate, and utilizing a lower cost processing technique to fabricate the portionin the non-semiconductor substrate. The portionsandare coupled to yield the MEMS structure, and the MEMS structurecan be attached to another substrate as needed for additional functionality.

Microelectromechanical systems component and method of making same

An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a power amplifier, a second die having a capacitor, and a metal interconnect coupled to the power amplifier and the first capacitor. The metal interconnect has an inductance. The capacitor and metal interconnect form a shunt impedance.

Integrated matching networks and RF devices that include an integrated matching network

A deviceincludes substratesandcoupled to form a volumebetween the substrates. A surfaceof the substratefaces a surfaceof the substrate. A metal-insulator-metal capacitoris formed on one of the surfacesand. A conductive elementspans between a top electrodeof the capacitorand the other surfaceand. Viasandextend through the substrateand are electrically interconnected with the conductive elementand a bottom electrodeof the capacitor. Another deviceincludes an underpass transmission lineformed on a surfaceof a substratewithin a volumeformed between the substrateand another substrate. The lineunderlies an integrated deviceformed on a surfaceof the substrate

Integrated passive device and method of fabrication

Methods and apparatus are provided to enable a transceiver () or transmitter including a single PA line-up () to transmit signals having frequencies in two or more different frequency bands, and/or having two or more different modulation types, and/or having two or more different RF power levels. The single PA line-up includes at least one variable matching circuit () and a variable harmonic filter () to tune match and tune filter communication signals prior to transmission. The variable matching circuit and the variable harmonic filter each include at least one variable capacitive element (and) that switches ON/OFF depending on whether a low frequency signal or a high frequency signal is being transmitted. Each variable capacitive element includes separate direct current and radio frequency terminals to enable the single PA line-up to change signal modulation and/or RF power levels in addition to frequencies.

Re-configurable impedance matching and harmonic filter system

An integrated matching network and method for manufacturing an integrated matching network are provided. The method includes forming () a first die on a substrate, forming () a second die on the substrate, and forming () a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a PA (), a second die having a capacitor (), and a metal interconnect () coupled to the PA and the first capacitor. The metal interconnect () has an inductance. The capacitor () and metal interconnect () form a shunt impedance.

Integrated matching network and method for manufacturing integrated matching networks

An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.

Method for manufacturing a passive integrated matching network for power amplifiers

A method of making a semiconductor device includes the steps of: providing a semiconductor substrate () having a patterned interconnect layer () formed thereon; depositing a first dielectric material () over the interconnect layer; depositing a first electrode material () over the first dielectric material; depositing a second dielectric material () over the first electrode material; depositing a second electrode material () over the second dielectric material; patterning the second electrode material to form a top electrode () of a first capacitor (); and patterning the first electrode material to form atop electrode () of a second capacitor (), to form an electrode () of the first capacitor, and to define a resistor ().

Method of making a semiconductor device, and semiconductor device made thereby

Method of manufacturing a passive integrated matching network for power amplifiers

A semiconductor device and a method of making a semiconductor device. A damascene metal layer ( ) is formed in an insulating dielectric layer ( ), which is in direct electrical communication with a substrate ( ). A layer of a passive element, such as first capacitor electrode layer ( ) is disposed on metal layer ( ) and preferably is offset relative to metal layer ( ) to allow a direct electrical interconnect through a via ( ) to metal layer ( ). In one embodiment a capacitor and a resistor are formed as passive elements in the device. In another embodiment, the passive element includes at least one resistor ( ) and optionally a second resistor ( ). In yet another embodiment, metal layer ( ) is a damascene copper layer.

Growing community of inventors

Tempe, AZ, United States of America

Melvy Freeland Miller, Iii