Rockwell International Corporation

Melvin L Marmet

Clarence W Padgett

Mark R Tennyson

The invention applies a reference voltage to a responsive means for producing a signal of one type in the absence of a semi-conductor at the addressed memory location, and applies a voltage less than the reference voltage to the responsive means for producing a signal of another type if a semi-conductor is present at the addressed memory location. The reference voltage is produced by a novel constant low voltage variable current source. The responsive means comprises inverter amplifier means. The reference voltage centers the small voltage swing on the bit line to the trigger point of the inverter amplifier. The means for determining the magnitude of voltage applied to the inverter is a pull up FET in series with the memory FET at the addressed location. If the electrical resistance of the FETs is similar, one half of the reference voltage will be applied to the inverter and it produces an off, or nearly off, type signal indicating presence; otherwise in the absence of a memory FET, full reference voltage is applied to the inverter to produce an on type signal indicating absence. Thus, the sense amplifier is independent of any reference voltage tracking the midpoint of the small bit line swing, and it is faster, requires less die area and restores full MOS output from a one volt signal swing.

FET Power supply for MOS memories

A circuit for producing a signal of one type in the absence of a semiconductor at an addressed memory location and a signal of another type in the presence of the semiconductor includes a constant voltage reference source to supply a variable current to a pull up FET. The pull up FET is connected to be in series with the memory semiconductor when it is present in the circuit, and operates to supply a low level voltage to an output amplifier when the semiconductor is present and a high level voltage when the semiconductor is not present. The low level voltage is centered about the trigger point of the amplifier, so that the bit line swing from the memory semiconductor produces a full MOS output from the amplifier.

Sense amplifier and method for small bit line swing with short

A static read only memory fabricated with field effect transistors of either the depletion type or the enhancement type connected in series. The read only memory includes a compact sensing circuit for detecting relatively small voltage swings at each node corresponding to a bit line of the memory cell, and a highly sensitive differential sense amplifier including first and second cascaded connected inverter stages.

Static read only memory

An improved static metal oxide semiconductor (MOS) input circuit having particular utility as a TTL input receiver, is fabricated from enhancement and depletion-type field effect transistors (FETs). The input circuit is adapted to produce positive feedback to adjust the on-resistance ratios of some of the circuit transistor devices, whereby hysteresis is developed. By virtue of the hysteresis, an extended noise margin is provided at the circuit input terminal so that MOS logic level output signals are clearly distinguishable from one another at the circuit output terminal.

Metal oxide semiconductor (MOS) input circuit with hysteresis

An improved high gain, field effect transistor differential amplifier including first and second cascade connected inverter stages, a feedback controlled source of current connected to each of the stages, including a source of controlled positive feedback for increasing the voltage gain. A positive feedback path is connected between an output terminal of the differential amplifier and the source of current so that the current in each inverter stage is more precisely controlled.

High gain differential amplifier with positive feedback

A Y address decoder used in conjunction with an X-Y matrix array, high density read-only memory unit, that reduces the number of series FET stages in the electrical path needed to evaluate the logic state of an addressed cell location of such a read-only memory unit. The reduction is achieved by gating logic in which the signal stored in the evaluated cell location, is derived from the output terminals of a tier of decoders, the appropriate decoder being connected directly to an output driver by a gate-controlled switch. The gate signal to render each such switch conductive is generated by an AND-OR circuit in repsonse to a unique Y address code, thereby obviating the otherwise time-consuming requirement for the evaluation signal to flow through additional tiers of decoders.

Growing community of inventors

Corona, CA, United States of America

Melvin L Marmet