Cirrus Logic Inc.

Melvin L Hagge

John L Melanson

Johann Guy Gaboriau

Lingli Zhang

Edmund Mark Schneider

Adrian Maxim

Baker Scott, Iii

Vamsikrishna Parupalli

Brian David Trotter

Jianping Wen

Mikel Ash

A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of a plurality of capacitor networks has a plurality of sampling capacitors for sampling over a plurality of sampling sub-phases an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC comprising a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.

Successive approximation register analog-to-digital converter with multiple sample capacitors

A pulse width modulation system including a pulse width modulation stage for generating a pulse width modulated signal in response to an input signal and an other pulse width modulation stage for generating an other pulse width modulated signal in response to an other input signal. Additional circuitry ensures that transitions of the pulse width modulated signal and the other pulse width modulated signal are spaced in time by a selected amount for small levels of the input signal.

Circuits and methods for reducing noise and distortion in pulse width modulation systems

A pulse width modulation circuit for driving a full-bridge output load includes a pulse width modulation stage for generating, from an input data stream, a pulse width modulated data stream for driving a terminal of a full-bridge output load and another pulse width modulated data stream for driving another terminal of the full bridge output load. A delay circuit delays the another pulse width modulated data stream relative to the pulse width modulated data stream such that edges of the another pulse width modulated data stream and edges of the pulse width modulated data stream are temporally spaced.

Circuits and methods for reducing distortion and noise in pulse width modulation systems utilizing full-bridge drivers

A centered-pulse consecutive edge modulation (CEM) method and apparatus provides a pulse output that advantageously exploits the full edge update rate of the CEM while providing substantially centered pulses. The method and apparatus also operate without substantial delay in the input control path. The apparatus includes a delta-sigma noise shaping modulator followed by a CEM that receives an output of the delta-sigma modulator quantizer. A non-linear correction signal is applied with polarity alternating at each edge and is applied to the quantizer input or is designed into the quantizer transfer function. The non-linear correction signal compensates for the noise-shaping modulator output such that the expected rising edge and falling edge widths of the CEM output pulses are substantially equal with respect to a DC input to the delta-sigma modulator.

Centered-pulse consecutive edge modulation (CEM) method and apparatus

A loop filter device and method for implementing a loop filter for a phase locked loop (&ldquo;PLL&rdquo;) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.

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Round Rock, TX, United States of America

Melvin L Hagge