Cray Research, Inc.

Melvin C August

Eugene F Neumann

Stephen A Bowen

Stephen E Nelson

Richard R Steitz

John T Williams

James N Kruchowski

Gregory W Pautsch

Stephen Cermak, Iii

Mary A Nebel

Diane M Christie

Eugene N Reshanov

David Collins

Daniel C Mansur

Eric J Mueller

Max C Logan

Richard J Kelley

Daniel Massopust

Lloyd T Shepherd

Steven J Dean

Albert H Wilson

Perry D Franz

Delvin D Eberlein

Ram K Gupta

Arthur Joseph Hebert

David L Duxstad

Paul E Schroeder

Peter J Wehner

Deanna M Dowdle

Steven S Chen

M Dean Roush

Danny J Cunagin

John B Eder

Danny J Cunnigan

Larry W Gullickson

Lester T Davis

David F Leonard

Lars Herlufsen

Paul M Knudsen

Louis Saye

Dean B Dudley

A completely shielded metallized connector block for use in multiple circuit modules of an electronic device. Electrical communication between the circuit boards is effected by an array of metallic pins which run through the blocks. The metallization on the nonconductive blocks can be held at ground or at a constant potential to increase the shielding between pins as well as maintaining voltage and ground planes at constant levels throughout the modules. The metallization is insulated from the pins and circuit boards by nonconductive bushings inserted in holes in the blocks. In one embodiment, the metallization consists of copper and solder plating and the blocks are constructed of liquid crystal polymer.

Method of manufacturing metallized connector block

A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.

Method of fabricating metallized chip carries from wafer-shaped

A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by 'opening' the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

Integrated circuit chip carrier lid

Computer cabinet

A completely shielded metallic connector block for use in multiple circuit modules of an electronic device. Electrical communication between the circuit boards is effected by an array of metallic pins which run through the blocks. The metal of the blocks can be held at ground or at a constant potential to increase the shielding between pins as well as maintaining voltage and ground planes at constant levels throughout the modules. The blocks are insulated from the pins and circuit boards by a non-conductive coating. In the preferred embodiment, the metal of the blocks is aluminum and the coating is a hardcoat anodizing.

Method of manufacturing metal connector blocks

Metallized connector block

A hermetically sealed carrier for integrated circuits has an IC placed on a carrier substrate, and an electrical lead apparatus, comprised of a highly heat resistant substrate with a metallized interconnect pattern deposited thereon, connected to the IC and brought out across and over the edges of the carrier substrate to facilitate electrical connection to a circuit board. A lid is provided which is placed over the IC. A low-melting temperature adhesive means is then placed on the lid-to-carrier interface and is exposed to heat hermetically sealing the IC. A hermetically sealed carrier including a single silicon die which includes both an active region where an integrated circuit may be fabricated and an inactive region is also provided. Electrical leads are electrically interconnected to the IC of the active region and extend to the periphery of the inactive region of the silicon die. A lid and adhesive means is provided for hermetically sealing the IC of the active region.

Non-metallized chip carrier

The present invention provides an improved method for manufacturing circuit boards with high power, high density interconnects. Printed circuit board technology, integrated circuit technology, and heavy-build electroless plating are combined to produce multilayer circuit boards comprised of substrates with different interconnect densities. In the higher density substrates, thick metallized layers are built-up by combining additive and subtractive techniques. These thicker foils minimize DC voltage drop so that conductors can run for longer distances. The conductors are substantially more square than their thin film equivalents, thus providing better performance for high frequency signals. Power distribution capabilities are enhanced by the present invention, so that circuit boards fully populated with dense, high-speed, high-power integrated circuits can easily be supplied with their necessary power requirements.

High power, high density interconnect apparatus for integrated circuits

Method of fabricating metallized chip carriers from wafer-shaped

Shielded connector block

Apparatus and method for determining the electrical length of a signal flow path, such as a twisted-pair conductor, to create conductors of the same electrical length are disclosed. The term electrical length refers to a certain physical distance for a length of conductor for which an electrical signal travels, or propagates along the conductor, in a specified amount of time. The apparatus preferably includes a Time Domain Reflectometer 25 (including pulse generator means 30 and electrical response display means 20) which is cooperatively connected to a first end of a conductor pair 51 under test. The conductor pair 51 is inserted through a ground plane 60 or other impedance changing device. Means to mark or cut 62 the conductor 51 are located within the ground plane 60 or as close as possible to the point at which the impedance is changed. Processing means 40 are utilized to adjust the conductor 51 length relative to the ground plane 60. In operation, the pulse generator means 30 sends a pulse along the conductor 51. The ground plane 60 reflects a portion of the pulse back to the electrical response display means 20 with the signal propagation delay per unit mechanical length being calculated thereby.

Method and apparatus for optimizing the electrical length of a signal

An optical backplane interconnects logic assemblies in a computer system using optical fibers. The logic assembly is connected to a laser or LED for converting electrical signals from the logic assembly into the equivalent optical signals. The optical signals are transmitted along the optical fibers to another logic assembly. The optical backplane comprises a mainframe rail for mounting to one end of the logic assembly, a connector attached to the mainframe rail, and an optical coupler mated with the connector. The optical coupler and connector having matching vee grooves for supporting and aligning the optical fibers.

Computer signal interconnect apparatus

A ceramic chip carrier package for integrated circuits is described which provides reduced interlead capacitance. A cavity for the placement of the integrated circuit chip is centrally located on a substrate. The leads of the package are bridged between the cavity and the outer periphery of the substrate. The leads are bonded to the substrate using adhesive glass placed on the substrate at the outer periphery of the cavity and at the outer periphery of the substrate. Sealing glass is placed on the outer periphery of the substrate over the leads to provide a bonding material for a lid to the package. The area between the cavity and the outer periphery of the substrate has no adhesive or sealing glass which thus provides an air dielectric between the leads so that interlead capacitance is reduced. In a second preferred embodiment, a channel is provided in the ceramic substrate between the periphery of the cavity and the periphery of the substrate to control the flow of adhesive glass and sealing glass so that the glasses do not migrate onto the leads. Since the air dielectric constant is lower than the glass dielectric constant, the interlead capacitance is lower than that found in prior art packages.

Reduced capacitance chip carrier

Growing community of inventors

Chippewa Falls, WI, United States of America

Melvin C August