University of Southern California

Melvin A Breuer

Peter A Beerel

Benmao Cheng

Dylan Hand

Navnit K Nanda

An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.

Timing violation resilient asynchronous template

Thorough delay testing of a combinational logic circuit is accomplished by changing only one input at a time (a single transition), and checking the output at a predetermined short time later, and arrangements are disclosed for systematically applying to the inputs of a combinational logic circuit all possible single transitions of the binary input signals. One economical test circuit uses a conventional binary counter and an associated ring counter to generate the test signals, in addition to input switching circuits or multiplexers for steering data to the logic to be tested and control circuitry to control the test process.

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Encino, CA, United States of America

Melvin A Breuer